On 28/07/17 17:21, Nanley Chery wrote:
On Fri, Jul 28, 2017 at 09:28:45AM +0100, Lionel Landwerlin wrote:
On 19/07/17 22:21, Nanley Chery wrote:
Cc:
Suggested-by: Jason Ekstrand
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_blorp.c | 8
src/intel/vulkan
Both patches are :
Reviewed-by: Lionel Landwerlin
On 14/07/17 07:14, Jason Ekstrand wrote:
This will allow us to keep everything in one place when it comes to
declaring what extensions are supported.
---
src/intel/Makefile.vulkan.am| 3 +-
src/intel/vulkan
Since this is available from 1.0.57, do we need to bump the supported
API version first?
On 01/08/17 17:02, Jason Ekstrand wrote:
There is literally no work for us to do here. It already just works in
our driver.
---
src/intel/vulkan/anv_device.c | 4
1 file changed, 4 insertions(+)
d
On 01/08/17 19:54, Jason Ekstrand wrote:
The VkVersion class is probably overkill but it makes it really easy to
compare versions in a way that's safe without the caller having to think
about patch vs. no patch.
---
src/intel/vulkan/anv_entrypoints_gen.py | 4 +--
src/intel/vulkan/anv_extensi
Patches 1, 3, 4 & 5 are:
Reviewed-by: Lionel Landwerlin
On 01/08/17 19:54, Jason Ekstrand wrote:
This way we can use "from anv_extensions import *" in the entrypoint
generator without worrying too much about pollution
---
src/intel/vulkan/anv_entrypoints_gen.py | 4 ++--
sr
On 01/08/17 23:33, Jason Ekstrand wrote:
On Tue, Aug 1, 2017 at 2:03 PM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
Since this is available from 1.0.57, do we need to bump the
supported API version first?
I don't think it really matters
Rb then :)
On 01/08/17 23:32, Jason Ekstrand wrote:
On Tue, Aug 1, 2017 at 2:07 PM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
On 01/08/17 19:54, Jason Ekstrand wrote:
The VkVersion class is probably overkill but it makes it
really easy to
c
Both are :
Reviewed-by: Lionel Landwerlin
On 02/08/17 02:16, Jason Ekstrand wrote:
Unreal Engine 4 seems to really like VK_FORMAT_R8_SRGB for some reason.
We don't technically have the hardware format but we do have L8_SRGB.
It's easy enough to fake with that and a swizzle. While w
Hi,
What prompted me to dig into this was that we didn't seem the decode
the ImmediateData field of MI_STORE_DATA_IMM properly. The fix for
this is in patch 6. I also found out that we were skipping printing
some dword with fields > 32bits.
Cheers,
Lionel Landwerlin (7):
intel: decode
Stall At Pixel Scoreboard: false
Depth Cache Flush Enable: false
0x000ce138: 0x : Dword 2
Address: 0x
0x000ce140: 0x : Dword 4
Immediate Data: 0
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 10 ++
1 file changed, 6
The xml files don't always have fields in order. This might confuse
our parsing of the commands. Let's have the fields in order. To do
this, the easiest way it to use a linked list. It also helps a bit
with the iterator.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_deco
Length: 2
Store Qword: 0
Use Global GTT: false
0x000ce0b8: 0x00045010 : Dword 1
Core Mode Enable: 0
Address: 0x00045010
0x000ce0bc: 0x : Dword 2
0x000ce0c0: 0x : Dword 3
Immediate Data: 0
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c
Due to the new way we handle fields, we need *not* to forget the first
field when decoding instructions. The issue was that the advance
function was called first and skipped the first field.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 31
This should be inside the function that actually decodes fields.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index a30b7f28aab
Making the next change more readable.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index e32d4190235
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 48d4456cc16..2c4eaab1701 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/.gitignore b/src/intel/vulkan/.gitignore
index 725a8584624..4ea978d6e41 100644
--- a/src/intel/vulkan/.gitignore
+++ b/src/intel/vulkan/.gitignore
@@ -1,4 +1,5
Signed-off-by: Lionel Landwerlin
---
src/intel/isl/isl_format_layout.csv | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/isl/isl_format_layout.csv
b/src/intel/isl/isl_format_layout.csv
index f340e30a1bf..150c15220eb 100644
--- a/src/intel/isl/isl_format_layout.csv
+++ b/src
Acked-by: Lionel Landwerlin
I can see that it fixes the tests and it makes sense, but I'm failing to
see how gl_attrib_wa_flags ends up being set from anv :/
Thanks a lot!
On 21/07/17 09:26, Iago Toral Quiroga wrote:
Mesa will map user defined vertex input attributes to slots
starti
On 04/08/17 18:24, Jason Ekstrand wrote:
---
src/intel/vulkan/anv_batch_chain.c | 57 +--
src/intel/vulkan/anv_device.c | 1 +
src/intel/vulkan/anv_gem.c | 36
src/intel/vulkan/anv_private.h | 23 +
src/intel/vul
On 04/08/17 18:24, Jason Ekstrand wrote:
Vulkan allows you to do a submit whose only job is to wait on and
trigger semaphores. The easiest way for us to support that right
now is to insert a dummy execbuf.
---
src/intel/vulkan/anv_batch_chain.c | 28 +---
src/intel/vul
This series is :
Reviewed-by: Lionel Landwerlin
I have a couple of nits, feel free to ignore.
Thanks!
On 04/08/17 18:24, Jason Ekstrand wrote:
This series is a quick re-spin of the v2 sent yesterday to address review
feedback from Chris. In particular, we now set EXEC_ASYNC on the trivial
This enables us to compile aubinator without the libdrm dependency.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/intel_aub.h | 153
1 file changed, 153 insertions(+)
create mode 100644 src/intel/tools/intel_aub.h
diff --git a/src/intel
es.
I've only included the minimal set of header files we need from the
kernel for anv & i965. Maybe other drivers would be interested and
maybe we should put all the kernel drm uapi headers into include?
Cheers,
Lionel Landwerlin (2):
aubinator: import intel_aub.h from libdrm
anv/i965:
On 27/04/17 08:20, Eric Anholt wrote:
Emil Velikov writes:
On 25 April 2017 at 23:56, Lionel Landwerlin
wrote:
Hi,
While working with changes that span from kernel to user space, I've
been wondering whether we need to depend on libdrm at all for the anv
& i965 drivers. Indeed w
The application might not give an output structure.
CID: 1405765 (Null pointer dereferences)
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_formats.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
This series is :
Reviewed-by: Lionel Landwerlin
On 03/05/17 19:44, Kenneth Graunke wrote:
Newer Mesa requires this. It's irrelevant for us; pretend to have it.
---
intel_stub.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/intel_stub.c b/intel_s
Reviewed-by: Lionel Landwerlin
On 03/05/17 19:46, Kenneth Graunke wrote:
When running shader-db with intel_stub and recent Mesa, context creation
fails when making a logical hardware context. In this case, we call
intelDestroyContext(), which gets here and tries to unmap the cache BO.
But
On 04/05/17 07:52, Emil Velikov wrote:
On 4 May 2017 at 14:46, Daniel Vetter wrote:
On Thu, Apr 27, 2017 at 10:58:42AM -0700, Lionel Landwerlin wrote:
On 27/04/17 08:20, Eric Anholt wrote:
Emil Velikov writes:
On 25 April 2017 at 23:56, Lionel Landwerlin
wrote:
Hi,
While working with
Something funny happened with the indentation, if you could fix this,
this is :
Reviewed-by: Lionel Landwerlin
Thanks!
-
Lionel
On 04/05/17 17:34, Grazvydas Ignotas wrote:
ping
Emil: the code this fixes is yours.
Gražvydas
On Tue, May 2, 2017 at 8:17 PM, Grazvydas Ignotas <mailto:n
Reviewed-by: Lionel Landwerlin
On 07/05/17 23:48, Eric Engestrom wrote:
Fixes: ddb99127a6f6c ("egl/x11: Honor the EGL_PLATFORM_X11_SCREEN_EXT
attribute")
Signed-off-by: Eric Engestrom
---
src/egl/main/egldisplay.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff -
A couple of straightforward changes to silence coverity warnings.
Lionel Landwerlin (2):
anv: avoid null pointer dereference
anv: check return value of anv_execbuf_add_bo
src/intel/vulkan/anv_batch_chain.c | 9 +++--
src/intel/vulkan/anv_formats.c | 3 ++-
2 files changed, 9
CID: 1405919 (Error handling issues)
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_batch_chain.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/anv_batch_chain.c
index 6d6babadea1..9def174b429
The application might not give an output structure.
CID: 1405765 (Null pointer dereferences)
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_formats.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
We should get either 0 or 1 here.
CID: 1373562 (Control flow issues)
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 15bba3274ed
CID: 1399477, 1399478 (Integer handling issues)
Signed-off-by: Lionel Landwerlin
Cc: Matt Turner
---
src/intel/compiler/brw_eu_validate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_eu_validate.c
b/src/intel/compiler/brw_eu_validate.c
index
Going through a few more warnings that seem relevant.
Cheers,
Lionel Landwerlin (3):
intel: gen decoder: don't check for size_t negative values
intel: compiler: remove duplicated code
intel: compiler: prevent integer overflow
src/intel/common/gen_decoder.c | 2 +-
src/
CID: 1399470: (Control flow issues)
Signed-off-by: Lionel Landwerlin
Cc: Matt Turner
---
src/intel/compiler/brw_eu_validate.c | 12
1 file changed, 12 deletions(-)
diff --git a/src/intel/compiler/brw_eu_validate.c
b/src/intel/compiler/brw_eu_validate.c
index f231ea038b4
Reviewed-by: Lionel Landwerlin
On 10/05/17 01:12, Rafael Antognolli wrote:
Use an alias for this field on 3DSTATE_INDEX_BUFFER on gen6+, so we can set
the same value as the defines.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen6.xml | 1 +
src/intel/genxml/gen7.xml | 1
Reviewed-by: Lionel Landwerlin
On 10/05/17 01:12, Rafael Antognolli wrote:
Several issues were caught on review after the original patch landed.
This commit fixes them.
v2:
- Fix padding (Topi)
- Remove .DestinationElementOffset change from this patch (Topi)
Signed-off-by: Rafael
Reviewed-by: Lionel Landwerlin
On 10/05/17 01:12, Rafael Antognolli wrote:
Emit the respective commands using genxml code.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri/i965/gen7_cs_state.c | 162
Reviewed-by: Lionel Landwerlin
On 10/05/17 01:12, Rafael Antognolli wrote:
Also make the brw_get_index_type() function not shift its return, since that
is genxml's job now.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_context.h | 6 ++--
src/mesa/driver
Reviewed-by: Lionel Landwerlin
On 10/05/17 01:12, Rafael Antognolli wrote:
With this last state ported, we can get rid of gen8_draw_upload.c.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_state.h | 1
On 11/05/17 12:27, Tapani Pälli wrote:
On 05/11/2017 02:23 PM, Emil Velikov wrote:
On 1 May 2017 at 12:09, Mauro Rossi wrote:
Fixes the following building error happening on marshmallow-x86
with Ubuntu 16.04 LTS stock build essentials package
and by the book Android build system.
external/m
On 11/05/17 13:58, Lionel Landwerlin wrote:
On 11/05/17 12:27, Tapani Pälli wrote:
On 05/11/2017 02:23 PM, Emil Velikov wrote:
On 1 May 2017 at 12:09, Mauro Rossi wrote:
Fixes the following building error happening on marshmallow-x86
with Ubuntu 16.04 LTS stock build essentials package
and
On 05/05/17 17:47, Daniel Stone wrote:
Calling random callbacks on the display's event queue is hostile, as
we may call into client code when it least expects it. Create our own
event queue, one per wsi_wl_display, and use that for the registry.
Signed-off-by: Daniel Stone
Cc: mesa-sta...@lists
In the unlikely case the parsing of genxml files fails, we were
leaking an xml parser object.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common
Reported-by: Mauro Rossi
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index
v2: Just use cast to uintptr_t (Chris)
Reported-by: Mauro Rossi
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src/mesa/drivers/dri
Fixes a build issue with gallium headers trying to include llvm ones
(which I don't have installed).
Thanks!
Tested-by: Lionel Landwerlin
On 10/11/17 17:23, Dylan Baker wrote:
Using build_by_default : false is convenient for dependencies that can
be pulled in by various diverse componen
Reviewed-by: Lionel Landwerlin
On 11/11/17 00:55, Kenneth Graunke wrote:
We renamed "Function Enable" to "Enable", which broke our detection
of whether shaders are enabled or not. So, we'd see a bunch of HS/DS
packets with program offsets of 0, and think that wa
:(
The intention was to deal with cases where we've encountered more than
MAX_NUM_PROGRAMS (actually happened to me).
So we start by the index + 1 assuming this is the oldest program because
we're in a rolling window of programs.
This is obviously broken with the < 4096 programs case. Maybe w
has one and this will trigger a segfault.
We might be better off taking it out. Otherwise, looks good :
Reviewed-by: Lionel Landwerlin
+ if (iter_more_fields(iter)) {
+ iter->field = iter->field->next;
+ } else {
if (!iter_more_groups(iter))
ret
].gtt_offset == instr_base_address) {
Is it a guarantee that the instruction buffer is going to be given in
its own section?
Or do we need to check bounds ?
if (instr_base_address >= sections[s].gtt_offset && inst_base_address <=
sections[s].gtt_offset + sections[s].count * 4)
Ot
I think I sneaked the exact same fix in
f5e5ca1e210c2e0f505ea154ca553275157dda73 (bottom of the patch).
Reviewed-by: Lionel Landwerlin
On 12/11/17 08:35, Kenneth Graunke wrote:
while loops skip the first field of the instruction/structure, which
is not what the code intended. It works out
On 12/11/17 08:35, Kenneth Graunke wrote:
This is a bit more annoying than your average shader - we need to look
at MEDIA_INTERFACE_DESCRIPTOR_LOAD in the batch buffer, then hop over
to the dynamic state buffer to read the INTERFACE_DESCRIPTOR_DATA, then
hop over to the instruction buffer to deco
Reviewed-by: Lionel Landwerlin
On 12/11/17 23:43, Jason Ekstrand wrote:
They serve no purpose other than to just fill empty space in the packet
so each dword has something. Just disallowing empty groups is a bit
easier on some of the tools. This does not change the generated packing
headers
On 13/11/17 13:17, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/common/gen_decoder.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 8b00b6edc2..e3b2457dfd 10064
This allows us to deploy new configurations without touching the
kernel.
v2: Detect loadable configs without creating one (Chris)
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 109 --
1 file changed, 101 insertions(+), 8 deletions
There was a mistake just in those metric sets. We probably didn't
noticed because they're not really interesting for 3D workloads.
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_oa_bdw.xml| 4 ++--
src/mesa/drivers/dri/i965/brw_oa_kblgt2.xml | 4 ++--
src/me
This provides a good way to verify we haven't broken using the perf
driver on older kernels (which don't have the oa config loading
mechanism).
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h
Just fixing names.
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_oa_bdw.xml| 50 ++---
src/mesa/drivers/dri/i965/brw_oa_bxt.xml| 26 +++
src/mesa/drivers/dri/i965/brw_oa_glk.xml| 26 +++
src/mesa/drivers/dri/i965
(allowed by 3)
Cheers,
Lionel Landwerlin (8):
i965: perf: update configs for loading from userspace
i965: perf: add support for userspace configurations
i965: add a debug option to disable oa config loading
i965: perf: update counter names on gen8/9 platforms
i965: fix time elapsed counter
When making configs loadable from userspace in the kernel, we left to
userspace more responsability around programming some registers. In
particular one register we use to set directly in the driver has now
been moved into the configs.
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_oa_bdw.xml| 183 +++
src/mesa/drivers/dri/i965/brw_oa_bxt.xml| 160
src/mesa/drivers/dri/i965/brw_oa_kblgt2.xml | 164
src/mesa/drivers/dri/i965
Some of the big patches got caught.
You can find this series here :
https://github.com/djdeath/mesa/tree/wip/djdeath/oa-userspace-configs
-
Lionel
On 13/11/17 14:58, Lionel Landwerlin wrote:
Hi,
Although the main point of this series is to add performance queries
for Coffeelake. This series
On 13/11/17 22:59, Kenneth Graunke wrote:
On Sunday, November 12, 2017 3:57:56 AM PST Lionel Landwerlin wrote:
On 12/11/17 08:35, Kenneth Graunke wrote:
This makes aubinator_error_decode's shader dumping work like aubinator.
Instead of printing them after the fact, it prints them right i
On 13/11/17 21:40, Kenneth Graunke wrote:
On Sunday, November 12, 2017 4:06:06 AM PST Lionel Landwerlin wrote:
On 12/11/17 08:35, Kenneth Graunke wrote:
This is a bit more annoying than your average shader - we need to look
at MEDIA_INTERFACE_DESCRIPTOR_LOAD in the batch buffer, then hop over
> @@ -586,6 +587,8 @@ init_fast_clear_state_entry(struct
anv_cmd_buffer *cmd_buffer,
> sdi.ImmediateData = 0;
> }
> }
> +
> + addr += 4;
Aparently, I didn't compile-test this because I need a .offset here. :/
Heh, I was confused too :)
With that fixed :
Reviewed-by:
Oh dear...
Reviewed-by: Lionel Landwerlin
On 13/11/17 16:12, Jason Ekstrand wrote:
Otherwise, if the image is not bound to the start of the buffer, we're
going to be reading and writing its fast clear state in the wrong spot.
Cc: mesa-sta...@lists.freedesktop.org
---
src/intel/v
Reviewed-by: Lionel Landwerlin
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Reviewed-by: Lionel Landwerlin
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Reviewed-by: Lionel Landwerlin
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, level, layer, format, resolve_op);
+ prepare_ccs_resolve(batch, ¶ms, surf, level, start_layer,
+ format, resolve_op);
+ params.num_layers = num_layers;
Ohoh... Was num_layers uninitialized before this patch?
Otherwise looks good :
Reviewed-by: Lionel Landwerlin
Reviewed-by: Lionel Landwerlin
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On 13/11/17 16:12, Jason Ekstrand wrote:
There are enough #ifs in there that it's kind-of pointless to duplicate
it for each buffer.
---
src/intel/blorp/blorp_genX_exec.h | 69 +++
1 file changed, 33 insertions(+), 36 deletions(-)
diff --git a/src/intel/blo
Reviewed-by: Lionel Landwerlin
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On 13/11/17 16:12, Jason Ekstrand wrote:
This is a bit complicated because we have to get the indirect clear
color in there somehow. In order to not do any more work in the shader
than needed, we set it up as it's own vertex binding which points
directly at the clear color address specified by t
Reviewed-by: Lionel Landwerlin
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I thought I sent a Rb on this one...
Reviewed-by: Lionel Landwerlin
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On 16/11/17 08:36, Kenneth Graunke wrote:
Original 965 sets bits 28:27 to 0, while G45 and later set it to 1.
Also, there's no GPGPU pipeline on Gen5, and the pipeline to select
is a single bit - bit 1 is reserved.
Are you sure you haven't mixed them?
---
src/intel/genxml/gen45.xml | 4 ++-
On 16/11/17 08:36, Kenneth Graunke wrote:
Original 965 sets bits 28:27 to 0, while G45 and later set it to 1.
Also, there's no GPGPU pipeline on Gen5, and the pipeline to select
is a single bit - bit 1 is reserved.
Are you sure you haven't mixed them?
---
src/intel/genxml/gen45.xml | 4 ++-
rc/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index 93e687a32bd..8fdac7cd55a 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -1253,13 +1253,12 @@
-
+
With the part below dropped :
Reviewed-b
Hi,
We do the same things in i965 to notify the kernel about buffers of
interest in case of GPU hang. Let's do it in Anv too!
Cheer,
Lionel Landwerlin (2):
anv: setup BO flags at state_pool/block_pool creation
anv: flag batch & instruction BOs for capture
src/intel/vulkan/anv_al
When the kernel support flagging our BO, let's mark batch &
instruction BOs for capture so then can be included in the error
state.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_device.c | 6 --
src/intel/vulkan/anv_private.h | 1 +
2 files changed, 5 insertions(+), 2
This will allow to set the flags on any anv_bo created/filled from a
state pool or block pool later.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_allocator.c | 24 --
src/intel/vulkan/anv_device.c | 18
src
On 17/11/17 17:57, Kristian Høgsberg wrote:
On Fri, Nov 17, 2017 at 9:48 AM, Lionel Landwerlin
wrote:
When the kernel support flagging our BO, let's mark batch &
instruction BOs for capture so then can be included in the error
state.
Signed-off-by: Lionel Landwerlin
---
src/int
On 17/11/17 18:37, Kenneth Graunke wrote:
On Friday, November 17, 2017 9:47:59 AM PST Lionel Landwerlin wrote:
This will allow to set the flags on any anv_bo created/filled from a
state pool or block pool later.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_allocator.c
Reviewed-by: Lionel Landwerlin
On 18/11/17 00:55, Kristian H. Kristensen wrote:
Signed-off-by: Kristian H. Kristensen
---
src/intel/genxml/gen_pack_header.py | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/intel/genxml/gen_pack_header.py
b
Trying to detect cases where we read/write at the wrong offsets in
images.
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103197
---
src/tests/func/renderpass/clear.c | 235 ++
1 file changed, 235 insertions(+)
diff
Reviewed-by: Lionel Landwerlin
On 26/11/17 09:27, Kenneth Graunke wrote:
We want to program the 3DSTATE_RASTER field to the gl_context value,
not the other way around.
Fixes: 13ac46557ab1 (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.)
---
src/mesa/drivers/dri/i965/genX_state_upload.c
Reviewed-by: Lionel Landwerlin
On 26/11/17 10:09, Kenneth Graunke wrote:
These were moved to src/intel/common/gen_debug.h, but they are not
common code. They assume that brw_context or gl_context variables
exist, named brw or ctx. That isn't remotely true outside of i965.
---
src/
Hash maps might use pointer keys (which people surely might want to
use to hash values) in which case a 0 value is perfectly acceptable.
It's only if the hash function needs to deference the pointer that we
want to be sure it's not NULL.
Signed-off-by: Lionel Landwerlin
---
block (Ian)
Signed-off-by: Lionel Landwerlin
---
src/util/hash_table.c | 4 ++--
src/util/hash_table.h | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/util/hash_table.c b/src/util/hash_table.c
index b7421a0144c..8a4de565fcc 100644
--- a/src/util/hash_table.c
+++
Taken from drm-next ca797d29cd63e7b71b4eea29aff3b1cefd1ecb59
Signed-off-by: Lionel Landwerlin
---
include/drm-uapi/README | 8 +++---
include/drm-uapi/drm.h | 41 ++
include/drm-uapi/drm_mode.h | 70 +++--
include/drm
The reference value in gen_device_info isn't going to be acurate on
Gen10+. We should query it from the kernel, which reads a couple of
register to compute the actual value.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_device.c | 13 +
1 file changed, 13 inser
p-get
spec@ext_timer_query@time-elapsed
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/intel_screen.c | 24
1 file changed, 24 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index db1552
.
We introduced a new parameter to query in the kernel to expose that
information. This seems like it's going to land in 4.16. Here are the
userspace patches making use of that new param.
Cheers,
Lionel Landwerlin (3):
drm-uapi: Update drm/i915 headers from drm-next
i965: read CS timestamp freq
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