This is currently not needed but will be necessary when we have
features that do not work with DCC enabled, such as image stores
and sharing non-scanout surfaces.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeonsi/si_blit.c | 31 +--
src/gallium
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon/r600_texture.c | 5 +
src/gallium/drivers/radeonsi/cik_sdma.c | 3 ++-
src/gallium/drivers/radeonsi/si_blit.c| 3 ++-
src/gallium/drivers/radeonsi/si_dma.c | 3 ++-
4 files changed, 11 insertions(+), 3 deletions
As the alignment requirements can be 32 KiB or more, also adding
an aligned buffer creation function.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon/r600_buffer_common.c | 21 +++
src/gallium/drivers/radeon/r600_pipe_common.h | 6
src/gallium/drivers/radeon
Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR
still works. Furthermore, with DCC compression we can directly clear
to a limited set of colors such that we do not need a postprocessing step.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeon/r600_texture.c | 2 ++
src/gallium/drivers/radeon/r600d_common.h | 1 +
src/gallium/drivers/radeonsi/si_descriptors.c | 5
src/gallium/drivers/radeonsi/si_pipe.h
Needed for various DCC related operations. As invalidating the L2
cache seems unnecesary, this introduces a new flag to flush the cache
without invalidating the L2 cache.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi
Add a mask to track if a texture level is still in its decompressed
state or that we would need to decompress again.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeon/r600_texture.c | 1 +
src/gallium/drivers/radeonsi
on is DCC compressed.
- Only set ALPHA_IS_ON_MSB when needed.
- Rework compression tracking and decompress to be optional.
Bas Nieuwenhuizen (7):
radeonsi: Allocate buffers for DCC.
radeonsi: Disable operations that do not work with DCC.
radeonsi: Add a CACHE_FLUSH event
radeonsi: Enabl
anymore for rendering.
Do we still want patch 6 and 7 or should I drop them until we have an
actual user?
Yours sincerely,
Bas Nieuwenhuizen
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
, Xonotic regresses for me if I enable DCC for scanout
surfaces.
Yours sincerely,
Bas Nieuwenhuizen
On Mon, Oct 12, 2015 at 10:27 PM, Axel Davy wrote:
> On 12/10/2015 17:05, Bas Nieuwenhuizen wrote:
>>
>> Hi Marek,
>>
>> Thanks for the quick review.
>>
>>
der MSAA resolve if the destination is DCC compressed.
- Only set ALPHA_IS_ON_MSB when needed.
- Rework compression tracking and decompress to be optional.
Bas Nieuwenhuizen (7):
radeonsi: Allocate buffers for DCC.
radeonsi: Disable operations that do not work with DCC.
radeo
As the alignment requirements can be 32 KiB or more, also adding
an aligned buffer creation function.
DCC is disabled for textures that can be shared as sharing the
DCC buffers has not been implemented yet.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon/r600_buffer_common.c
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon/r600_texture.c | 5 +
src/gallium/drivers/radeonsi/cik_sdma.c | 3 ++-
src/gallium/drivers/radeonsi/si_blit.c| 3 ++-
src/gallium/drivers/radeonsi/si_dma.c | 3 ++-
4 files changed, 11 insertions(+), 3 deletions
Add a mask to track if a texture level is still in its decompressed
state or that we would need to decompress again.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeon/r600_texture.c | 1 +
src/gallium/drivers/radeonsi
Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR
still works. Furthermore, with DCC compression we can directly clear
to a limited set of colors such that we do not need a postprocessing step.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon
This is currently not needed but will be necessary when we have
features that do not work with DCC enabled, such as image stores
and sharing non-scanout surfaces.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeonsi/si_blit.c | 31 +--
src/gallium
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeon/r600_texture.c | 2 ++
src/gallium/drivers/radeon/r600d_common.h | 1 +
src/gallium/drivers/radeonsi/si_descriptors.c | 5 +++
src/gallium/drivers/radeonsi/si_pipe.h
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeonsi/si_state_draw.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index ce6c98c..29c40d2 100644
--- a/src/gallium/drivers
On Wed, Oct 21, 2015 at 9:56 AM, Axel Davy wrote:
> On 21/10/2015 00:10, Bas Nieuwenhuizen wrote:
>>
>>
>> DCC is disabled for textures that can be shared as sharing the
>> DCC buffers has not been implemented yet.
>>
>>
>> + surf->dcc_ena
On Wed, Oct 21, 2015 at 12:28 PM, Axel Davy wrote:
> +/* This flag indicates that in addition to being shared, the resource won't
> be
> + * read by any external process before we call flush_resource. This allows
> + * things like compressing the buffer when drawing, while uncompressing on
> + *
My apologies, wrong term. I meant the front buffer of the X server in
the non-compositing case.
- Bas
On Wed, Oct 21, 2015 at 1:26 PM, Axel Davy wrote:
> On 21/10/2015 13:16, Bas Nieuwenhuizen wrote:
>>
>> On Wed, Oct 21, 2015 at 12:28 PM, Axel Davy wrote:
>>>
>>
On Thu, Oct 22, 2015 at 12:12 PM, Marek Olšák wrote:
> On Wed, Oct 21, 2015 at 12:10 AM, Bas Nieuwenhuizen
> wrote:
>> Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR
>> still works. Furthermore, with DCC compression we can directly clear
>> to
On Thu, Oct 22, 2015 at 12:12 PM, Marek Olšák wrote:
>> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
>> b/src/gallium/drivers/radeonsi/si_descriptors.c
>> index 5548cba3..a277fa5 100644
>> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
>> +++ b/src/gallium/drivers/radeonsi/si_d
On Fri, Oct 23, 2015 at 12:50 PM, Marek Olšák wrote:
> On Fri, Oct 23, 2015 at 12:17 PM, Bas Nieuwenhuizen
> wrote:
>> On Thu, Oct 22, 2015 at 12:12 PM, Marek Olšák wrote:
>>>> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
>>>> b/src/galli
On Fri, Oct 23, 2015 at 1:52 PM, Marek Olšák wrote:
> On Fri, Oct 23, 2015 at 1:30 PM, Bas Nieuwenhuizen
> wrote:
>> On Fri, Oct 23, 2015 at 12:50 PM, Marek Olšák wrote:
>>> On Fri, Oct 23, 2015 at 12:17 PM, Bas Nieuwenhuizen
>>> wrote:
>>>> On Thu, Oc
On Fri, Oct 23, 2015 at 4:57 PM, Marek Olšák wrote:
> On Fri, Oct 23, 2015 at 1:57 PM, Bas Nieuwenhuizen
> wrote:
>> On Fri, Oct 23, 2015 at 1:52 PM, Marek Olšák wrote:
>>> On Fri, Oct 23, 2015 at 1:30 PM, Bas Nieuwenhuizen
>>> wrote:
>>>> On Fri, Oc
Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR
still works. Furthermore, with DCC compression we can directly clear
to a limited set of colors such that we do not need a postprocessing step.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeon
Had someone that tried --with-vulkan-drivers=radv, this will guide
people in the right direction.
Signed-off-by: Bas Nieuwenhuizen
CC:
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index b35adc8a3aa..57fd4075dc0 100644
--- a
On Fri, Jan 27, 2017, at 10:31, Emil Velikov wrote:
> On 27 January 2017 at 18:14, Bas Nieuwenhuizen
> wrote:
> > Had someone that tried --with-vulkan-drivers=radv, this will guide
> > people in the right direction.
> >
> It might be better to update the help stri
And this time I need to check my mail before sending ;)
Reviewed-by: Bas Nieuwenhuizen
On Fri, Jan 27, 2017, at 19:31, Emil Velikov wrote:
> From: Emil Velikov
>
> Analogous to what we do for the dri and gallium drivers.
>
> Cc: 17.0 13.0
> Cc: Bas Nieuwenhuizen
>
Apparently the source is not an address but an offset, so we actually
need to use the base.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common
ation for LLVMPipe.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_llvm_util.c| 12
src/amd/common/ac_llvm_util.h| 3 +++
src/amd/common/ac_nir_to_llvm.c | 2 +-
src/gallium/drivers/llvmpipe/lp_jit.c| 8 +++-
src/gallium/drivers/rad
vm 3.4 or 3.5. Meaning you don't need a
> ifdef for the radeon drivers.
> Or ist there any disadvantage of this versus the older method?
>
> Roland
>
> Am 28.01.2017 um 17:40 schrieb Bas Nieuwenhuizen:
> > Since LLVM revision 293359 DumpModule gets only implemented w
ation for LLVMPipe.
v2: Use the new code for LLVM 3.4+ instead of LLVM 5+ & fixed indentation
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_llvm_util.c| 8
src/amd/common/ac_llvm_util.h| 3 +++
src/amd/common/ac_nir_to_llvm.c | 2 +-
sr
Based on code written by Dave Airlie.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_binary.c | 30 +++---
src/amd/common/ac_binary.h | 4 +++-
src/amd/common/ac_llvm_util.c | 4 ++--
src/amd/common/ac_llvm_util.h | 2 +-
src/amd/common
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 187 -
src/amd/vulkan/radv_pipeline.c | 11 +--
src/amd/vulkan/radv_private.h | 8 ++
3 files changed, 200 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 6 ++-
src/amd/vulkan/radv_radeon_winsys.h | 1 +
src/amd/vulkan/radv_wsi.c | 2 +-
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 62 +--
4 files
Based on code written by Dave Airlie.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 22 +++-
src/amd/vulkan/radv_device.c | 23
src/amd/vulkan/radv_pipeline.c | 75
src/amd/vulkan/radv_private.h
v2: Create the descriptor BO with CPU access.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 186 -
src/amd/vulkan/radv_pipeline.c | 11 +--
src/amd/vulkan/radv_private.h | 8 ++
3 files changed, 199 insertions(+), 6 deletions
Patch 1-3, 6-7 are
Reviewed-by: Bas Nieuwenhuizen
The other two you'll need to find someone else to review as I'm not
going to review my own patches.
- Bas
On Fri, Jan 27, 2017, at 06:03, Andres Rodriguez wrote:
> ---
> src/amd/vulkan/radv_device.c | 4
> 1 file ch
Reviewed-by: Bas Nieuwenhuizen
On Mon, Jan 30, 2017, at 04:28, Dave Airlie wrote:
> From: Dave Airlie
>
> It appears we can get image barriers like:
> srcStageMask: VkPipelineStageFlags = 4096
> (VK_PIPELINE_STAGE_TRANSFER_BIT)
>
Reviewed-by: Bas Nieuwenhuizen
On Mon, Jan 30, 2017, at 07:14, Dave Airlie wrote:
> From: Dave Airlie
>
> We weren't adding the fragment position properly.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_nir_to_llvm.c | 11 ++-
> 1 file changed,
g_size = 0;
> struct radeon_winsys_cs *preamble_cs = NULL;
> VkResult result;
>
> @@ -1222,10 +1397,12 @@ VkResult radv_QueueSubmit(
> scratch_size = MAX2(scratch_size,
> cmd_buffer->scratch_size_needed);
> co
Pushed, thanks.
On Mon, Jan 30, 2017, at 22:26, Robert Foss wrote:
> Prevent Coverity seeing potential errors when src is
> no initialized in the switch case.
>
> Coverity-Id: 1396397
> Signed-off-by: Robert Foss
> ---
>
> Patch can be found here:
>
> https://git.collabora.com/cgit/user/robe
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jan 31, 2017, at 01:38, Dave Airlie wrote:
> From: Dave Airlie
>
> There are some corner cases where you end up with an esgs ring, but no
> gsvs ring, test for both before dereferencing.
>
> Fixes:
> dEQP-VK.geometry.emit.points_emi
this line.
Reviewed-by: Bas Nieuwenhuizen
> ---
> src/amd/common/ac_nir_to_llvm.c | 20 +++-
> 1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c
> b/src/amd/common/ac_nir_to_llvm.c
> index 0e629de..e04a5cc 1006
On Tue, Jan 31, 2017, at 06:24, Dave Airlie wrote:
> From: Dave Airlie
>
> The CTS tests at least are using this, and we were totally
> ignoring it.
>
> This hopefully fixes the bouncing multisample CTS tests.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 8 --
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 2 +-
src/amd/vulkan/radv_pipeline.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 06fefb3779e..d45c71c0e61 100644
--- a/src/amd/vulkan
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 173 ++--
1 file changed, 129 insertions(+), 44 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c22529741fa..1b23a065633 100644
--- a/src
No f16 support as I'm not quite sure about alignment yet.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c1bbb00184b..74976b3e222 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 101 +++-
1 file changed, 48 insertions(+), 53 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 657f38626e7..c1bbb00184b 100644
--- a/src
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 75 +++--
1 file changed, 49 insertions(+), 26 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 74976b3e222..f8d0e8ab366 100644
--- a/src
Patches 1 and 2 are
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jan 31, 2017, at 16:00, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/compiler/spirv/nir_spirv.h | 1 +
> src/compiler/spirv/spirv_to_nir.c | 4
> src/compiler/spirv/vtn_v
A basic implementation of VK_KHR_shader_draw_parameters. I haven't
bothered with optimizing it away in the case the shader doesn't
use it, but the impact seems low anyway.
Needs the first two patches of Lionel's series for the driver
independent support.
Bas Nieuwenhuizen (3):
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 4
src/amd/vulkan/radv_pipeline.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index da67b65ef43..0c8af823263 100644
--- a/src/amd/vulkan/radv_device.c
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 091d970ee0b..97c6b63ce01 100644
--- a/src/amd/vulkan
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c622c006cec..132150139c7 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b
On Wed, Feb 1, 2017, at 00:48, Dave Airlie wrote:
> From: Dave Airlie
>
> The CTS tests at least are using this, and we were totally
> ignoring it.
>
> This hopefully fixes the bouncing multisample CTS tests.
>
> v2: get family mask in ignored case from command buffer.
>
> Signed-off-by: Dav
Reviewed-by: Bas Nieuwenhuizen
On Wed, Feb 1, 2017, at 01:25, Dave Airlie wrote:
> From: Dave Airlie
>
> The CTS tests at least are using this, and we were totally
> ignoring it.
>
> This hopefully fixes the bouncing multisample CTS tests.
>
> v2: get family mask in i
Patches 1-2 are
Reviewed-by: Bas Nieuwenhuizen
On Wed, Feb 1, 2017, at 02:12, Dave Airlie wrote:
> From: Dave Airlie
>
> This fixes clip distance fetches as they are single item loads
> with a const_index like float[1].
>
> Fixes:
> dEQP-VK.clipping.user_defined.*.vert_g
For the series:
Reviewed-by: Bas Nieuwenhuizen
On Thu, Feb 2, 2017, at 00:15, Dave Airlie wrote:
> From: Dave Airlie
>
> These are all reuseable by radv.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_llvm_util.c| 154 ++
Reviewed-by: Bas Nieuwenhuizen
On Thu, Feb 2, 2017, at 00:19, Dave Airlie wrote:
> From: Dave Airlie
>
> This migrates to the code shared with radeonsi.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_nir_to_llvm.c | 128
> +-
For the series:
Reviewed-by: Bas Nieuwenhuizen
On Thu, Feb 2, 2017, at 00:41, Dave Airlie wrote:
> From: Dave Airlie
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_nir_to_llvm.c | 44
> ++---
> 1 file changed, 2 insert
For the series:
Reviewed-by: Bas Nieuwenhuizen
On Thu, Feb 2, 2017, at 00:56, Dave Airlie wrote:
> From: Dave Airlie
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_nir_to_llvm.c | 75
> -
> 1 file changed, 7 insert
Reviewed-by: Bas Nieuwenhuizen
On Fri, Feb 3, 2017, at 02:04, Dave Airlie wrote:
> From: Dave Airlie
>
> These regressed and caused doom to stop loading.
>
> Fixes:
> 03724af26 radv/ac: Implement Float64 load/store var.
>
> Signed-off-by: Dave Airlie
> ---
> s
the 0.255 range
> > but the vec2 are aligned inside vec4 slots. So scale the indir index,
> > then extract the channels.
> >
> > This appears to fix DOOM for me.
>
> Looks like appearances were deceiving, doom isn't fully fixed by this.
>
You are not the
Reviewed-by: Bas Nieuwenhuizen
On Fri, Feb 3, 2017, at 04:30, Dave Airlie wrote:
> From: Dave Airlie
>
> We count the number of slots used, but slots are vec4 sized,
> so we have to scale by 16 not 4.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_nir_to
On Fri, Feb 3, 2017, at 19:24, Jason Ekstrand wrote:
> On Fri, Feb 3, 2017 at 9:23 AM, Samuel Pitoiset
> wrote:
>> This is similar to the MESA_GLSL_VERSION_OVERRIDE envvar (mainly
>> for developers). But this one has the advantage to be configured
>> for specific apps which require a context
%)
Failed:0/2981 (0.0%)
Not supported: 1720/2981 (57.7%)
Warnings: 0/2981 (0.0%)
As well as no regressions in the complete CTS.
Bas Nieuwenhuizen (8):
radv/amdgpu: Allow submitting 0 command buffers.
radv: Better handle submitting 0 command buffers.
radv/amdgpu: Add
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 22 --
src/amd/vulkan/radv_private.h | 1 +
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 3f9a452ddf3..1e92046d62c 100644
If we had submitCount >0, but each submit had zero command buffers,
then we still wouldn't signal the fence.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_de
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_radeon_winsys.h | 5 +
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 218 +++---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h | 35 -
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 98
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 7 +--
src/amd/vulkan/radv_radeon_winsys.h | 1 +
src/amd/vulkan/radv_wsi.c | 3 ++-
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 12
4 files changed, 16
use-after-free. Implement
reference counting to avoid this.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 10 ++
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/src/amd/vulkan/winsys/amdgpu
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 75 +---
1 file changed, 71 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 1e92046d62c..d501be3793f 100644
--- a/src/amd
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_image.c | 23 +--
src/amd/vulkan/radv_private.h | 1 +
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 99d17376cf6..b6b5ccb04d8 100644
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index d501be3793f..4db58929a42 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd
On Mon, Feb 6, 2017, at 16:45, Eero Tamminen wrote:
> Hi,
>
> On 05.02.2017 15:19, Samuel Pitoiset wrote:
> > On 02/03/2017 07:48 PM, Bas Nieuwenhuizen wrote:
> >> As far as I can see[1], when the game detects GL 4.3+, the engine tries
> >> to load a different
Reviewed-by: Bas Nieuwenhuizen
On Mon, Feb 6, 2017, at 03:41, Dave Airlie wrote:
> From: Dave Airlie
>
> This fixes the vulkan samples deferredmultisampling test.
>
> Cc: "17.0"
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_nir_to_llvm.c | 3 +
CMASK alignment can be greater than image data alignment, so pass
it to the app so that it knows what alignment to backing memory
should have.
Signed-off-by: Bas Nieuwenhuizen
Cc:
---
src/amd/vulkan/radv_image.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/amd/vulkan/radv_image.c b
Works for me on dota2 and talos now.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 4 ++--
src/amd/vulkan/radv_meta_clear.c | 2 +-
src/amd/vulkan/radv_private.h| 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b
Signed-off-by: Bas Nieuwenhuizen
Cc: "17.0"
---
src/amd/vulkan/radv_image.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 202f460aafe..1581645b18d 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/ra
Yep,
Reviewed-by: Bas Nieuwenhuizen
On Tue, Feb 7, 2017, at 01:32, Dave Airlie wrote:
> From: Dave Airlie
>
> As was done for dcc and cmask.
>
> Cc: "17.0"
> Signed-off-by: Dave Airlie
> ---
> src/amd/vulkan/radv_image.c | 1 +
> 1 file changed, 1 i
On Tue, Feb 7, 2017, at 23:05, Dave Airlie wrote:
> From: Dave Airlie
>
> We need to initialize dcc like we do in the subpass path.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/vulkan/radv_meta_resolve.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/
Reviewed-by: Bas Nieuwenhuizen
On Wed, Feb 8, 2017, at 00:20, Dave Airlie wrote:
> From: Dave Airlie
>
> We need to initialize dcc like we do in the subpass path.
>
> v2: fix initial/final layouts
> Signed-off-by: Dave Airlie
> ---
> src/amd/vulkan/radv_meta_resolve
On Wed, Feb 8, 2017, at 10:10, Nicolai Hähnle wrote:
> On 05.02.2017 12:43, Bas Nieuwenhuizen wrote:
> > Signed-off-by: Bas Nieuwenhuizen
> > ---
> > src/amd/vulkan/radv_radeon_winsys.h | 5 +
> > src/amd/vulkan/winsys/am
On Wed, Feb 8, 2017, at 11:25, Matt Turner wrote:
> On Wed, Feb 8, 2017 at 12:31 AM, Timothy Arceri
> wrote:
> > On Tue, 2017-02-07 at 23:58 +0100, Matt Turner wrote:
> >> On Tue, Feb 7, 2017 at 4:42 AM, Timothy Arceri >> > wrote:
> >> > This series adds support for a GLSL IR level and TGSI (Op
For allowing fast color clears in the main render targets of dota2.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_formats.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index f18ecee9d2a
On Wed, Feb 8, 2017, at 23:33, Andres Rodriguez wrote:
>
>
> On 2017-02-08 12:19 PM, Bas Nieuwenhuizen wrote:
> > For allowing fast color clears in the main render targets of dota2.
> >
> > Signed-off-by: Bas Nieuwenhuizen
> > ---
> > src/amd/vulkan
Reviewed-by: Bas Nieuwenhuizen
I'll adjust the sparse binding patches.
On Thu, Feb 9, 2017, at 04:25, Dave Airlie wrote:
> From: Dave Airlie
>
> It's legal to submit just semaphores with no command streams,
> this patch fixes this case by emitting the empty cs, it al
ARY);
> -
> - cs_array[j] = cmd_buffer->cs;
> + if (cmd_buffer->no_draws == true) {
We never want to end up with 0 bo's if we have a fence or semaphores.
Maybe change the condition
Was thinking of a sort or other asymptotically more efficient merge
method, but in the meantime this is
Reviewed-by: Bas Nieuwenhuizen
On Fri, Feb 10, 2017, at 02:07, Dave Airlie wrote:
> From: Dave Airlie
>
> Just noticed we do a fair bit of unneeded searching here.
>
> Sin
The struct have different size, so the arrays have different stride.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 45 +++-
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan
On Sat, Feb 11, 2017, at 13:03, Timothy Arceri wrote:
>
>
> On 10/02/17 21:43, Nicolai Hähnle wrote:
> > On 07.02.2017 04:42, Timothy Arceri wrote:
> >> From: Timothy Arceri
> >>
> >> This will be used to store all pointers in the cache as 64bit ints
> >> allowing us to avoid issues when a 32b
Reviewed-by: Bas Nieuwenhuizen
On Sun, Feb 12, 2017, at 20:11, Dave Airlie wrote:
> From: Dave Airlie
>
> If a buffer is just full of flushes we flush things on command
> buffer submission, so don't bother submitting these.
>
> This will reduce some CPU overhead on dota
Series is
Reviewed-by: Bas Nieuwenhuizen
On Mon, Feb 13, 2017, at 05:15, Dave Airlie wrote:
> From: Dave Airlie
>
> This puts the common gfx state for the device into an
> indirect buffer, and just calls out to it, on CIK and above.
>
> This is taken from what radeonsi doe
Reviewed-by: Bas Nieuwenhuizen
On Mon, Feb 13, 2017, at 20:55, Dave Airlie wrote:
> From: Dave Airlie
>
> This uses the common fs interp code to use the new
> llvm intrinsics so llvm can drop the old ones.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/comm
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Mon, Feb 13, 2017, at 23:15, Dave Airlie wrote:
> From: Dave Airlie
>
> This uses the common code to emit the correct intrinsic.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_nir_to_llvm.c | 30 --
Series is:
Reviewed-by: Bas Nieuwenhuizen
On Tue, Feb 14, 2017, at 07:10, Dave Airlie wrote:
> From: Dave Airlie
>
> On some CIK (Hawaii) this needs to be at least 64k, I'm not 100% sure
> it doesn't need to be 128k.
>
> This was causing fast clear eliminate to o
1 - 100 of 2366 matches
Mail list logo
