Re: [Mesa-dev] [PATCH v3 2/3] mesa/st: enable EXT_sRGB_write_control for drivers that support it

Am Freitag, den 19.10.2018, 14:27 -0400 schrieb Ilia Mirkin: > On Fri, Oct 19, 2018 at 12:45 PM Gert Wollny om> wrote: > > > > Am Freitag, den 19.10.2018, 08:25 -0400 schrieb Ilia Mirkin: > > > I don't think a PIPE_CAP is the answer here... I think you're on > > > the right track with format chec

[Mesa-dev] [Bug 108508] Graphic glitches with stream output support on OLAND AMD GPU GCN 1.0

https://bugs.freedesktop.org/show_bug.cgi?id=108508 --- Comment #3 from Ahmed Elsayed --- Thanks. Where is the mailing list? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mail

[Mesa-dev] [Bug 108508] Graphic glitches with stream output support on OLAND AMD GPU GCN 1.0

https://bugs.freedesktop.org/show_bug.cgi?id=108508 --- Comment #4 from Ahmed Elsayed --- I am sorry. You mean mesa-dev@lists.freedesktop.org ? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.__

Re: [Mesa-dev] [PATCH] intel: Fix decoding for partial STATE_BASE_ADDRESS updates.

Could you maybe update src/intel/tools/aubinator_viewer_decoder.cpp (function handle_state_base_address) ? Either way : Reviewed-by: Lionel Landwerlin On 22/10/2018 06:18, Kenneth Graunke wrote: STATE_BASE_ADDRESS only modifies various bases if the "modify" bit is set. Otherwise, we want to

Re: [Mesa-dev] [PATCH 0/6] nir: Cleanups for opt_algebraic

With the typo fix on patch 5/6 suggested by Matt, this patch series is: Reviewed-by: Samuel Iglesias Gonsálvez Sam On Saturday, 20 October 2018 20:01:28 (CEST) Jason Ekstrand wrote: > This little series provides some cleanups for opt_algebraic. The most > important of which is adding descripti

Re: [Mesa-dev] [PATCH 0/9] nir: Add better helpers for handling constant sources

Patch 7/9 has never arrived my inbox and checking the archives [0], looks like the archive is messed up... it has only a few emails. Does somebody know what happened with the ML archive? Sam [0] https://lists.freedesktop.org/archives/mesa-dev/2018-October/date.html On Saturday, 20 October 2018

Re: [Mesa-dev] [PATCH] intel/compiler: Change src1 reg type to unsigned doubleword

On 20/10/18 3:25, Sagar Ghuge wrote: > To have uniform behavior while disassembling send(c) instruction use > register type of unsigned doubleword for src1 when message descriptor is > immediate value. Bspec does not specifiy anything for src1 immediate s/specifiy/specify With that fixed and as

[Mesa-dev] [PATCH 06/28] spirv/nir: include row major coming from SPIR-V on the glsl type

--- src/compiler/spirv/spirv_to_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 28f4716b40e..52c3c968bb7 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -743,6 +743,7 @@

[Mesa-dev] [PATCH 04/28] spirv/nir: fill up nir variable info for ubos and ssbo

Some nir variables are only filled up for some specific modes. We found to need the binding for ubos/ssbos. The comment before that code (starts with XXX) points that binding still needs to be filled up for uniform variables at that point, and that should be fixed, although it doesn't specify why

[Mesa-dev] [PATCH 00/28 v3] ARB_gl_spirv: v3 ubo/ssbo support, plus CTS goodness

This is the third version of the ubo/ssbo support for ARB_gl_spirv. It is mostly a v2 resend, rebased against master, and small tweaks to fix minor rebase conflicts. Just to remember: * AOA of ubo/ssbo not included. Will be supported on a future series. * This series include two patch

[Mesa-dev] [PATCH 07/28] spirv/nir: don't set interface_type if it is not a struct

vnt_variables uses interface_type on several use cases, but on nir variable it is more limited. From nir.h: /** * For variables that are in an interface block or are an instance of an * interface block, this is the \c GLSL_TYPE_INTERFACE type for that block. * * \sa ir_varia

[Mesa-dev] [PATCH 01/28] spirv/nir: translate uniform blocks

They are supported by SPIR-V for ARB_gl_spirv. --- src/compiler/spirv/vtn_variables.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index cc3438bff23..3eb1e4e9c97 100644 --- a/src/compiler/spirv/vtn_

[Mesa-dev] [PATCH 03/28] spirv/nir: setting interface type for ubos/ssbos

Right now, a type is considered a ubo/ssbo if the mode is uniform/shader_storage and the interface_type is different to NULL. See ir_variable::in_in_buffer_block as an example. --- src/compiler/spirv/vtn_variables.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/sr

[Mesa-dev] [PATCH 02/28] spirv/nir: translate ssbo

They are supported by SPIR-V for OpenGL. OpenGL codepath expect nir to include the ssbo as nir variables. --- src/compiler/spirv/vtn_variables.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index 3e

[Mesa-dev] [PATCH 05/28] spirv/nir: include SPIR-V explicit offset on the glsl struct type

From ARB_gl_spirv spec: "Mapping of layouts std140/std430 -> explicit *Offset*, *ArrayStride*, and *MatrixStride* Decoration on struct members" and "A variable in the *Uniform* Storage Class decorated as a *Block* must be explicitly laid out using the *Offset*

[Mesa-dev] [PATCH 09/28] nir/types: add three new wrapper helpers

To already existing fields on glsl_types. Specifically: * glsl_get_struct_field_offset * glsl_get_struct_field_matrix_layout * glsl_type_arrays_of_arrays_size --- src/compiler/nir_types.cpp | 21 + src/compiler/nir_types.h | 8 2 files changed, 29 insertion

[Mesa-dev] [PATCH 08/28] spirv/nir: Handle location decorations on block interface members

From: Neil Roberts Previously the code was taking any location decoration on the block and using that to calculate the member locations for all of the members. I think this was assuming that there would only be one location decoration for the entire block. According to the Vulkan spec it is possi

[Mesa-dev] [PATCH 15/28] nir/linker/i965: Lower vulkan_resource_index during linking

From: Neil Roberts When linking a program using ARB_gl_spirv it now lowers the vulkan_resource_index intrinsic as an extra pass on the nir shader. Unlike Vulkan this can be done without waiting for the extra state from the pipeline layout. It also adds the call to this lowering on the i965 drive

[Mesa-dev] [PATCH 18/28] nir/linker: fill is_shader_storage for uniforms

--- src/compiler/glsl/gl_nir_link_uniforms.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/compiler/glsl/gl_nir_link_uniforms.c b/src/compiler/glsl/gl_nir_link_uniforms.c index 1a491dc2e5d..00995fb3f76 100644 --- a/src/compiler/glsl/gl_nir_link_uniforms.c +++ b/src/com

[Mesa-dev] [PATCH 16/28] nir/linker: handle non-ubo uses of vulkan_resource_index

From: Neil Roberts In order to replicate the behaviour of lower_ubo_reference_visitor, the lowering code should search the list of blocks in ShaderStorageBlocks for the matching binding whenever a non-ubo usage of the resource index is encountered. The intended usage of the vulkan_resource_index

[Mesa-dev] [PATCH 14/28] nir: add is_in_ubo/ssbo/block helpers

Equivalent to the already existing ir_variable is_in_buffer_block and is_in_shader_storage_block, adding the uniform buffer object one. I'm using the short forms (ssbo, ubo) to avoid having method names too long. --- src/compiler/nir/nir.h | 22 ++ 1 file changed, 22 insertions

[Mesa-dev] [PATCH 17/28] nir/linker: add gl_nir_link_uniform_blocks.c

Adding the ability to link uniform blocks and shader storage blocks using NIR, intended for ARB_gl_spirv support. Among other things, this linking needs to take into account that everything should work without names, as they could be not present, while the GLSL IR uniform block linking was wrote wi

[Mesa-dev] [PATCH 10/28] glsl_types/nir: add matrix_stride plus nir wrapper helpers

From ARB_gl_spirv spec: "7.6.2.spv SPIR-V Uniform Offsets and Strides The SPIR-V decorations *GLSLShared* or *GLSLPacked* must not be used. A variable in the *Uniform* Storage Class decorated as a *Block* must be explicitly laid out using the *Offset*, *ArrayStride*, and *Matr

[Mesa-dev] [PATCH 11/28] spirv/nir: fill glsl_struct_field explicit_matrix_stride

--- src/compiler/spirv/spirv_to_nir.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 52c3c968bb7..1201143d2f4 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -816,6 +81

[Mesa-dev] [PATCH 13/28] spirv/nir: fill glsl_type array stride

We need all the info when asking for the type, so we needed to call type_decoration_cb earlier, in order to get the ArrayStride. It is somewhat ugly to do this only for Array types, but we can't do it before the switch as type_decoration_cb have some asserts to ensure that the type and the decorat

[Mesa-dev] [PATCH 12/28] glsl_types/nir: add explicit_array_stride plus nir wrapper helpers

From ARB_gl_spirv: "Mapping of layouts std140/std430 -> explicit *Offset*, *ArrayStride*, and *MatrixStride* Decoration on struct members" That means that we would not have available any kind of layout info, and we should use explicit array strides. This comm

[Mesa-dev] [PATCH 20/28] nir/linker: fill up uniform_storage with explicit data

Specifically, offset, array_stride, matrix_stride and row_major. On GLSL, most of that info is computed, but on ARB_gl_spirv they are explicit, and for Mesa, included on the glsl_type. From ARB_gl_spirv spec: "Mapping of layouts std140/std430 -> explicit *Offset*, *ArrayStride*, and

[Mesa-dev] [PATCH 21/28] nir/linker: update already processed uniforms search for UBOs/SSBOs

Until now, we were using the uniform explicit location to check if the current nir variable already was processed, and entries on the uniform storage added. But for UBOs/SSBOs, entries are added but we lack a explicit location. For those we need to rely on the UBO/SSBO binding (to the nir variable

[Mesa-dev] [PATCH 19/28] nir/linker: use only the array element type for array of ssbo/ubo

For this interfaces, the inner members are added only once as uniforms or resources, in opposite to other cases, like a uniform array of structs. For those guessing why a issue (16) from ARB_program_interface_query was used, instead of a quote of the core spec: The core spec is not really clear ab

[Mesa-dev] [PATCH 22/28] nir/linker: Set the uniform's block_index

From: Antia Puentes Binding comparison is used to determine the block the uniform is part of. To do the binding comparison we need the information in UniformBlocks[] and ShaderStorageBlocks[] to be available, so we have to call gl_nir_link_uniform_blocks() before linking the uniforms. --- src/co

[Mesa-dev] [PATCH 23/28] nir/linker: add program ubo/ssbo at the resource list

--- src/compiler/glsl/gl_nir_linker.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/compiler/glsl/gl_nir_linker.c b/src/compiler/glsl/gl_nir_linker.c index 547549bc4e0..138a12e532d 100644 --- a/src/compiler/glsl/gl_nir_linker.c +++ b/src/compiler/glsl/gl_nir_linker.c @@

[Mesa-dev] [PATCH 25/28] i965: call to gl_nir_link_uniform_blocks

When using a SPIR-V shader. Note that needs to be done before linking uniforms, so when creating the uniform storage entries, block_index could be filled properly (among other things). --- src/mesa/drivers/dri/i965/brw_link.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drive

[Mesa-dev] [PATCH 27/28] mesa: add NULL name check for several length queries

Since ARB_gl_spirv it is possible to miss a lot of name reflection information, so it is needed to add NULL name checks for several queries, and return a specific value on those cases. This commit add them for ACTIVE_UNIFORM_BLOCK_MAX_NAME_LENGTH, ACTIVE_ATTRIBUTE_MAX_LENGTH and ACTIVE_UNIFORM_MAX_

[Mesa-dev] [PATCH 26/28] mesa: add NULL name check for NUM_ACTIVE_VARIABLES query

This can happens if we are running an SPIR-V shader (ARB_gl_spirv). --- src/mesa/main/shader_query.cpp | 30 -- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp index 11ecd71c575..b775b4231c2

[Mesa-dev] [PATCH 28/28] nir/linker: Add inputs/outputs to the program resource list

From: Antia Puentes --- src/compiler/glsl/gl_nir_linker.c | 79 +++ 1 file changed, 79 insertions(+) diff --git a/src/compiler/glsl/gl_nir_linker.c b/src/compiler/glsl/gl_nir_linker.c index 138a12e532d..acec0fe1f03 100644 --- a/src/compiler/glsl/gl_nir_linke

[Mesa-dev] [PATCH 24/28] i965: use GLboolean for all brw_link_shader returns

The function had a mix of true/GL_TRUE and false/GL_FALSE returns. Using GL_TRUE/GL_FALSE as the function returns a GLboolean. --- src/mesa/drivers/dri/i965/brw_link.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/dri

Re: [Mesa-dev] [PATCH 0/9] nir: Add better helpers for handling constant sources

Yeah... Bas said he had the same problem. The series can be found on my wip/nir-const-src branch of you want to see it that way. I can also resend if it's helpful. --Jason On October 22, 2018 06:31:01 Samuel Iglesias Gonsálvez wrote: Patch 7/9 has never arrived my inbox and checking the a

[Mesa-dev] [Bug 107865] swr fail to build with llvm-libs 6.0.1

https://bugs.freedesktop.org/show_bug.cgi?id=107865 Alok Hota changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Mesa-dev] [PATCH] radv: fix btoi for R32G32B32 when the dest offset is not 0

Fixes: 593996bc02 ("radv: implement buffer to image operations for R32G32B32") Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_bufimage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c

[Mesa-dev] [PATCH] meson: don't require libelf for r600 without LLVM

r600 doesn't have a hard requirement on LLVM, and therefore doesn't have a hard requirement on libelf. Currently the logic doesn't allow that however. Distro-bug: https://bugs.gentoo.org/669058 Fixes: 5060c51b6f4dfb0d5358bde6523285163d3faaad ("meson: build r600 driver") --- meson.build | 1

Re: [Mesa-dev] [PATCH] scons: Remove gles option.

Okay, I'll just leave it as "auto-off" on windows for now, with the toggle to explicitly turn it on if someone has a use case for that. Thanks, Dylan Quoting Jose Fonseca (2018-10-19 14:44:49) > > Jose, does it make more sense to just make gles on windows an error in > >meson? > > > I don't mi

Re: [Mesa-dev] [PATCH 0/9] nir: Add better helpers for handling constant sources

Re: The list. It doesn't always happen every month, but I've seen it multiple times now, as far back as January 2018, though possibly earlier. The gzip mail archive however has all the messages that are missing from the web archive. https://lists.freedesktop.org/archives/mesa-dev/2018-October.txt

Re: [Mesa-dev] [PATCH] intel/compiler: Change src1 reg type to unsigned doubleword

Thank you for reviewing the patch. On 10/22/18 5:02 AM, Samuel Iglesias Gonsálvez wrote: > > > On 20/10/18 3:25, Sagar Ghuge wrote: >> To have uniform behavior while disassembling send(c) instruction use >> register type of unsigned doubleword for src1 when message descriptor is >> immediate va

Re: [Mesa-dev] [PATCH] intel/compiler: Change src1 reg type to unsigned doubleword

On Mon, Oct 22, 2018 at 9:53 AM Sagar Ghuge wrote: > > Thank you for reviewing the patch. > > On 10/22/18 5:02 AM, Samuel Iglesias Gonsálvez wrote: > > > > > > On 20/10/18 3:25, Sagar Ghuge wrote: > >> To have uniform behavior while disassembling send(c) instruction use > >> register type of unsig

[Mesa-dev] [PATCH] vulkan/wsi: use the drmGetDevice2() API

From: Emil Velikov On older kernels, the drmGetDevice() call will wake up all the GPUs on the system, while fetching the PCI revision. Use the 2 version of the API and pass flags == 0, so we don't fetch the device PCI revision, since we don't need that information. Fixes: baa38c144f6 ("vulkan/w

Re: [Mesa-dev] [PATCH] vulkan/wsi: use the drmGetDevice2() API

On Mon, Oct 22, 2018 at 12:10 PM Emil Velikov wrote: > From: Emil Velikov > > On older kernels, the drmGetDevice() call will wake up all the GPUs > on the system, while fetching the PCI revision. > > Use the 2 version of the API and pass flags == 0, so we don't fetch the > device PCI revision, s

Re: [Mesa-dev] [PATCH] intel/eu: Don't apply chansel when repctrl is set

On Tue, Oct 16, 2018 at 4:57 PM Sagar Ghuge wrote: > Let's describe a little of why we're doing this and how we found it. If I recall correctly, we set a NOP (XYZW) swizzle on 3-src instructions, except we set an swizzle on LRP. Is that correct? > Signed-off-by: Sagar Ghuge > --- > src/in

Re: [Mesa-dev] [PATCH] intel/compiler: Print floating point values upto precision 8

On Fri, Oct 5, 2018 at 11:15 AM Sagar Ghuge wrote: > > avoid misinterpretation of encoded immediate values in instruction and > disassembled output. > > Signed-off-by: Sagar Ghuge > --- > While encoding the immediate floating point values in instruction we use > values upto precision 8, but while

Re: [Mesa-dev] [PATCH] meson: don't require libelf for r600 without LLVM

Thanks Dylan! Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 108508] Graphic glitches with stream output support on OLAND AMD GPU GCN 1.0

https://bugs.freedesktop.org/show_bug.cgi?id=108508 --- Comment #5 from Alex Deucher --- (In reply to Ahmed Elsayed from comment #4) > I am sorry. You mean mesa-dev@lists.freedesktop.org ? Correct. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee

Re: [Mesa-dev] [PATCH] meson: don't require libelf for r600 without LLVM

And pushed, thanks! Quoting Matt Turner (2018-10-22 10:40:36) > Thanks Dylan! > > Reviewed-by: Matt Turner signature.asc Description: signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/me

Re: [Mesa-dev] [PATCH] intel/eu: Don't apply chansel when repctrl is set

On 10/22/18 10:14 AM, Matt Turner wrote: > On Tue, Oct 16, 2018 at 4:57 PM Sagar Ghuge wrote: >> > > Let's describe a little of why we're doing this and how we found it. > If I recall correctly, we set a NOP (XYZW) swizzle on 3-src > instructions, except we set an swizzle on LRP. Is that c

Re: [Mesa-dev] [PATCH] intel: Fix decoding for partial STATE_BASE_ADDRESS updates.

On Monday, October 22, 2018 2:57:10 AM PDT Lionel Landwerlin wrote: > Could you maybe update src/intel/tools/aubinator_viewer_decoder.cpp > (function handle_state_base_address) ? > > Either way : > > Reviewed-by: Lionel Landwerlin Oops, good call, thanks! Pushed a v2 that updates both. sign

Re: [Mesa-dev] [PATCH 3/3] i965/miptree: Use cpu tiling/detiling when mapping

On Mon, Sep 24, 2018 at 4:20 AM Tapani Pälli wrote: > > From: Scott D Phillips > > Rename the (un)map_gtt functions to (un)map_map (map by > returning a map) and add new functions (un)map_tiled_memcpy that > return a shadow buffer populated with the intel_tiled_memcpy > functions. > > Tiling/deti

Re: [Mesa-dev] [PATCH] intel/compiler: Print floating point values upto precision 8

On 10/22/18 10:34 AM, Matt Turner wrote: > On Fri, Oct 5, 2018 at 11:15 AM Sagar Ghuge wrote: >> >> avoid misinterpretation of encoded immediate values in instruction and >> disassembled output. >> >> Signed-off-by: Sagar Ghuge >> --- >> While encoding the immediate floating point values in ins

[Mesa-dev] [PATCH 00/31] nir: Use a 1-bit data type for booleans

This is something that Connor and I have talked about quite a bit over the last couple of months. The core idea is to replace NIR's current 32-bit 0/-1 D3D10-style booleans with a 1-bit data type. All in all, I think it worked out pretty well though I really don't like the proliferation of 32-bit

[Mesa-dev] [PATCH 04/31] nir/builder: Add a nir_imm_true/false helpers

--- src/compiler/nir/nir_builder.h| 25 ++- src/compiler/nir/nir_lower_int64.c| 2 +- src/compiler/nir/nir_lower_returns.c | 4 +-- src/compiler/nir/nir_lower_subgroups.c| 2 +- src/compiler/nir/nir_opt_intrinsics.c | 2 +- s

[Mesa-dev] [PATCH 03/31] nir/constant_folding: Use nir_src_as_bool for discard_if

Missed one while converting to the nir_src_as_* helpers. --- src/compiler/nir/nir_opt_constant_folding.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index 05b47d4c0fe..5

[Mesa-dev] [PATCH 02/31] nir/constant_folding: Add an unreachable to a switch

--- src/compiler/nir/nir_opt_constant_folding.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index e2920e6b3fd..05b47d4c0fe 100644 --- a/src/compiler/nir/nir_opt_constant_folding.c +++ b/src/compile

[Mesa-dev] [PATCH 05/31] nir/builder: Handle 16-bit floats in nir_imm_floatN_t

--- src/compiler/nir/nir_builder.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 5ea0a5a2637..3271a480520 100644 --- a/src/compiler/nir/nir_builder.h +++ b/src/compiler/nir/nir_builder.h @@ -25,6 +25,7 @@

[Mesa-dev] [PATCH 01/31] nir/validate: Print when the validation failed

--- src/amd/vulkan/radv_shader.c | 4 +-- src/compiler/nir/nir.h| 12 +++ src/compiler/nir/nir_validate.c | 14 ++--- src/compiler/nir/tests/vars_tests.cpp | 38 +++ src/intel/compiler/brw_nir.c | 8 ++--- sr

[Mesa-dev] [PATCH 07/31] nir/opt_if: Rework condition propagation

Instead of doing our own constant folding, we just emit instructions and let constant folding happen. This is substantially simpler and lets us use the nir_imm_bool helper instead of dealing with the const_value's ourselves. --- src/compiler/nir/nir_opt_if.c | 91 -

[Mesa-dev] [PATCH 08/31] nir/system_values: Use the bit size from the load_deref

This isn't a great solution for bit-sizes but we don't have a particularly convenient way to get a bit size from the system value enum and this keeps the lowering pass from changing it. --- src/compiler/nir/nir_lower_system_values.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/

[Mesa-dev] [PATCH 06/31] nir/search: Use nir_builder

--- src/compiler/nir/nir_algebraic.py | 14 ++-- src/compiler/nir/nir_search.c | 111 -- src/compiler/nir/nir_search.h | 9 ++- 3 files changed, 43 insertions(+), 91 deletions(-) diff --git a/src/compiler/nir/nir_algebraic.py b/src/compiler/nir/nir_algebrai

[Mesa-dev] [PATCH 09/31] glsl/nir: Use i2b instead of ine for fixing UBO/SSBO booleans

They do the same thing in the end but i2b is a bit simpler. Also, let's clean up the mess of code for SSBO handling with one line of builder. --- src/compiler/glsl/glsl_to_nir.cpp | 24 +--- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/src/compiler/glsl/glsl_

[Mesa-dev] [PATCH 10/31] nir/prog: Use nir_bany in kill handling

We have a helper that does exactly what the bany_inequal was doing. It emits the same code but is a bit higher level and is designed to operate on a bvec4. --- src/mesa/program/prog_to_nir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/program/prog_to_nir.c b/src/m

[Mesa-dev] [PATCH 11/31] spirv: Use the right bit-size for spec constant ops

Previously, we would always pull the bit size from the destination which is wrong for opcodes like nir_ilt where the sources are variable-sized but the destination is a fixed size. We were getting lucky before because nir_op_ilt returns a 32-bit value and basically everyone who uses spec constants

[Mesa-dev] [PATCH 12/31] spirv: Initialize subgroup destinations with the destination type

Instead of initializing them manually, just use the type that we already have sitting there. --- src/compiler/spirv/vtn_subgroup.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/vtn_subgroup.c b/src/compiler/spirv/vtn_subgroup.c index ecec3aa62

[Mesa-dev] [PATCH 13/31] intel/nir: Use the OPT macro for more passes

--- src/intel/compiler/brw_nir.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 1cd56861578..cf5a4a96d67 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -674,7 +674,7 @@ brw

[Mesa-dev] [PATCH 22/31] nir: Add 1-bit boolean opcodes

--- src/compiler/nir/nir_lower_alu_to_scalar.c | 4 +++ src/compiler/nir/nir_opcodes.py| 29 ++ 2 files changed, 33 insertions(+) diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c b/src/compiler/nir/nir_lower_alu_to_scalar.c index e424dff25c4..4f97472a87d 1

[Mesa-dev] [PATCH 17/31] FIXUP: nir/algebraic: Remap boolean opcodes to the 32-bit variant

--- src/compiler/nir/nir_algebraic.py | 35 +++ 1 file changed, 35 insertions(+) diff --git a/src/compiler/nir/nir_algebraic.py b/src/compiler/nir/nir_algebraic.py index d2374d3216a..9d187ca36d7 100644 --- a/src/compiler/nir/nir_algebraic.py +++ b/src/compiler/nir/nir

[Mesa-dev] [PATCH 24/31] glsl,spirv: Generate 1-bit booleans

--- src/compiler/glsl/glsl_to_nir.cpp | 4 ++-- src/compiler/nir/nir.h| 2 +- src/compiler/nir/nir_opcodes_c.py | 8 src/compiler/nir_types.h | 4 +++- src/compiler/spirv/spirv_to_nir.c | 2 +- 5 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/compil

[Mesa-dev] [PATCH 16/31] FIXUP: nir/builder: Generate 32-bit bool opcodes transparently

--- src/compiler/nir/nir_builder_opcodes_h.py | 44 ++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_builder_opcodes_h.py b/src/compiler/nir/nir_builder_opcodes_h.py index e600093e9f6..a9de0e4ea47 100644 --- a/src/compiler/nir/nir_builder_

[Mesa-dev] [PATCH 23/31] nir: Add a bool to int32 lowering pass

We also enable it in all of the NIR drivers. Cc: Timothy Arceri Cc: Eric Anholt Cc: Rob Clark Cc: Bas Nieuwenhuizen --- src/amd/vulkan/radv_shader.c | 2 + src/broadcom/compiler/vir.c | 2 + src/compiler/Makefile.sources | 1 + src/com

[Mesa-dev] [PATCH 20/31] nir/constant_expressions: Rework boolean handling

This commit contains three related changes. First, we define boolN_t for N = 8, 16, and 64 and move the definition of boolN_vec to the loop with the other vec definitions. Second, there's no reason why we need the != 0 on the source because that happens implicitly when it's converted to bool. Th

[Mesa-dev] [PATCH 15/31] nir: Rename boolean-related opcodes to include 32 in the name

--- src/compiler/nir/nir_lower_alu_to_scalar.c | 8 ++-- src/compiler/nir/nir_opcodes.py| 46 +++--- src/compiler/nir/nir_opcodes_c.py | 8 ++-- 3 files changed, 31 insertions(+), 31 deletions(-) diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c b/src

[Mesa-dev] [PATCH 14/31] nir/algebraic: Disable b2f lowering and two optimizations

These all assume the 0/~0 representation of booleans. We'll turn them back on before too long. --- src/compiler/nir/nir_opt_algebraic.py | 5 - 1 file changed, 5 deletions(-) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 8b24daddfdc..5a4e78

[Mesa-dev] [PATCH 18/31] FIXUP: Use 32-bit opcodes in the NIR producers and optimizations

Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/n

[Mesa-dev] [PATCH 19/31] FIXUP: Use 32-bit opcodes in the NIR back-ends

Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/n

[Mesa-dev] [PATCH 21/31] nir: Add support for 1-bit data types

This commit adds support for 1-bit booleans and integers. Booleans obviously take a value of true or false. Because we have to define the semantics of 1-bit signed and unsigned integers, we define uint1_t to take values of 0 and 1 and int1_t to take values of 0 and -1. 1-bit arithmetic is then w

[Mesa-dev] [PATCH 27/31] FIXUP: nir/builder: Generate 1-bit booleans in nir_build_imm_bool

--- src/compiler/nir/nir_builder.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index eaba5cfe448..2f2fc49c448 100644 --- a/src/compiler/nir/nir_builder.h +++ b/src/compiler/nir/nir_builder.h @@ -212,9 +212,

[Mesa-dev] [PATCH 25/31] FIXUP: Revert "Use 32-bit opcodes in the NIR producers and optimizations"

--- src/compiler/nir/nir.h | 24 - src/compiler/nir/nir_loop_analyze.c| 28 +- src/compiler/nir/nir_opt_if.c | 2 +- src/compiler/nir/nir_opt_peephole_select.c | 2 +- src/compiler/nir/nir_opt_undef.c | 2 +- src/compiler/spirv/

[Mesa-dev] [PATCH 26/31] FIXUP: Revert "nir/builder: Generate 32-bit bool opcodes transparently"

--- src/compiler/nir/nir_builder_opcodes_h.py | 44 +-- 1 file changed, 1 insertion(+), 43 deletions(-) diff --git a/src/compiler/nir/nir_builder_opcodes_h.py b/src/compiler/nir/nir_builder_opcodes_h.py index a9de0e4ea47..e600093e9f6 100644 --- a/src/compiler/nir/nir_builder_

[Mesa-dev] [PATCH 28/31] nir/algebraic: Optimize 1-bit booleans

--- src/compiler/nir/nir_algebraic.py | 43 +++ src/compiler/nir/nir_opt_algebraic.py | 1 - 2 files changed, 4 insertions(+), 40 deletions(-) diff --git a/src/compiler/nir/nir_algebraic.py b/src/compiler/nir/nir_algebraic.py index 9d187ca36d7..b880aa0dc66 100644 ---

[Mesa-dev] [PATCH 29/31] nir/algebraic: Add back lower_b2f and a b2f optimization

--- src/compiler/nir/nir_opt_algebraic.py | 4 1 file changed, 4 insertions(+) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 6c767501a51..f0861c4411d 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++ b/src/compiler/nir/nir_opt_algebrai

[Mesa-dev] [PATCH 30/31] nir/algebraic: Add some optimizations for D3D-style booleans

D3D booleans use a 32-bit 0/-1 representation. Because this previously matched NIR exactly, we didn't have to really optimize for it. Now that we have 1-bit booleans, we need some specific optimizations to chew through the D3D12-style booleans. --- src/compiler/nir/nir_opt_algebraic.py | 13

[Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass

This should be useful for drivers that don't support real integers. Cc: Alyssa Rosenzweig --- src/compiler/Makefile.sources | 1 + src/compiler/nir/meson.build | 1 + src/compiler/nir/nir_lower_bool_to_float.c | 181 + 3 files changed, 183 inser

Re: [Mesa-dev] [PATCH] intel/compiler: Print floating point values upto precision 8

On Mon, Oct 22, 2018 at 2:14 PM Sagar Ghuge wrote: > > > > On 10/22/18 10:34 AM, Matt Turner wrote: > > On Fri, Oct 5, 2018 at 11:15 AM Sagar Ghuge wrote: > >> > >> avoid misinterpretation of encoded immediate values in instruction and > >> disassembled output. > >> > >> Signed-off-by: Sagar Ghug

Re: [Mesa-dev] [PATCH 06/31] nir/search: Use nir_builder

I think a better description is "nir/search: Use nir_imm_* helpers". Using nir_builder is just a prerequisite to doing that. On 10/22/2018 03:13 PM, Jason Ekstrand wrote: > --- > src/compiler/nir/nir_algebraic.py | 14 ++-- > src/compiler/nir/nir_search.c | 111 --

Re: [Mesa-dev] [PATCH 06/31] nir/search: Use nir_builder

On Mon, Oct 22, 2018 at 5:50 PM Ian Romanick wrote: > I think a better description is "nir/search: Use nir_imm_* helpers". > Using nir_builder is just a prerequisite to doing that. > Good call. The new commit message is: nir/search: Use the nir_imm_* helpers from nir_builder This requ

Re: [Mesa-dev] [PATCH 15/31] nir: Rename boolean-related opcodes to include 32 in the name

On 10/22/2018 03:13 PM, Jason Ekstrand wrote: > --- > src/compiler/nir/nir_lower_alu_to_scalar.c | 8 ++-- > src/compiler/nir/nir_opcodes.py| 46 +++--- > src/compiler/nir/nir_opcodes_c.py | 8 ++-- > 3 files changed, 31 insertions(+), 31 deletions(-) > > di

Re: [Mesa-dev] [PATCH 00/31] nir: Use a 1-bit data type for booleans

Patches 1 through 13 are Reviewed-by: Ian Romanick The rest are going to take a bit more time and deep thought. On 10/22/2018 03:13 PM, Jason Ekstrand wrote: > This is something that Connor and I have talked about quite a bit over the > last couple of months. The core idea is to replace NIR's

[Mesa-dev] [Bug 108508] Graphic glitches with stream output support on OLAND AMD GPU GCN 1.0

https://bugs.freedesktop.org/show_bug.cgi?id=108508 --- Comment #6 from Ahmed Elsayed --- Created attachment 142145 --> https://bugs.freedesktop.org/attachment.cgi?id=142145&action=edit Mafia III It gets better and better :D -- You are receiving this mail because: You are the assignee for th

Re: [Mesa-dev] [PATCH 30/31] nir/algebraic: Add some optimizations for D3D-style booleans

On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand wrote: > > D3D booleans use a 32-bit 0/-1 representation. Because this previously > matched NIR exactly, we didn't have to really optimize for it. Now that > we have 1-bit booleans, we need some specific optimizations to chew > through the D3D12-st

Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass

On Mon, Oct 22, 2018 at 6:16 PM Jason Ekstrand wrote: > > This should be useful for drivers that don't support real integers. > > Cc: Alyssa Rosenzweig > --- > src/compiler/Makefile.sources | 1 + > src/compiler/nir/meson.build | 1 + > src/compiler/nir/nir_lower_b

Re: [Mesa-dev] [PATCH 01/31] nir/validate: Print when the validation failed

Jason Ekstrand writes: > diff --git a/src/mesa/drivers/dri/i965/brw_program.c > b/src/mesa/drivers/dri/i965/brw_program.c > index f5ebd3c3b05..78050cda359 100644 > --- a/src/mesa/drivers/dri/i965/brw_program.c > +++ b/src/mesa/drivers/dri/i965/brw_program.c > @@ -91,14 +91,14 @@ brw_create_nir(s

Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass

For what it's worth, Midgard has real integers (including int32 support), using hardware-level D3D10 boolean conventions. I'm trying to wrap my head around how this interacts with 5d85a0a. I'm tempted to think the standard lower_bool_to_int32 pass would work, with an emulated b2f instruction in th

Re: [Mesa-dev] [PATCH 21/31] nir: Add support for 1-bit data types

On 10/22/2018 03:13 PM, Jason Ekstrand wrote: > This commit adds support for 1-bit booleans and integers. Booleans I've noticed this in some of the patches... Boolean is a proper name, so it should be capitalized everywhere. > obviously take a value of true or false. Because we have to define t

Re: [Mesa-dev] [PATCH 01/31] nir/validate: Print when the validation failed

On Mon, Oct 22, 2018 at 6:16 PM Eric Anholt wrote: > Jason Ekstrand writes: > > > diff --git a/src/mesa/drivers/dri/i965/brw_program.c > b/src/mesa/drivers/dri/i965/brw_program.c > > index f5ebd3c3b05..78050cda359 100644 > > --- a/src/mesa/drivers/dri/i965/brw_program.c > > +++ b/src/mesa/driver

Re: [Mesa-dev] [PATCH 14/31] nir/algebraic: Disable b2f lowering and two optimizations

On 10/22/2018 03:13 PM, Jason Ekstrand wrote: > These all assume the 0/~0 representation of booleans. We'll turn them > back on before too long. > --- > src/compiler/nir/nir_opt_algebraic.py | 5 - > 1 file changed, 5 deletions(-) > > diff --git a/src/compiler/nir/nir_opt_algebraic.py > b/s

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