[Mesa-dev] [PATCH 28/45] i965/fs: Use byte_scattered_write on 16-bit store_ssbo

We need to rely on byte scattered writes as untyped writes are 32-bit size. We could try to keep using 32-bit messages when we have two or four 16-bit elements, but for simplicity sake, we use the same message for any component number. We should revisit this in the future. --- src/intel/compiler/b

[Mesa-dev] [PATCH 29/45] i965/fs: Add byte scattered read message and fs support

From: Jose Maria Casanova Crespo --- src/intel/compiler/brw_eu.h| 7 + src/intel/compiler/brw_eu_defines.h| 2 ++ src/intel/compiler/brw_eu_emit.c | 41 ++ src/intel/compiler/brw_fs.cpp | 10 +++ src

[Mesa-dev] [PATCH 26/45] i965/fs: Add byte scattered write message and fs support

From: Jose Maria Casanova Crespo Signed-off-by: Jose Maria Casanova Crespo Signed-off-by: Alejandro Piñeiro --- src/intel/compiler/brw_eu.h| 6 ++ src/intel/compiler/brw_eu_defines.h| 17 + src/intel/compiler/brw_eu_emit.c | 89 +++

[Mesa-dev] [PATCH 31/45] compiler: Mark when input/ouput attribute at VS uses 16-bit

From: Jose Maria Casanova Crespo New shader attribute to mark when a location has 16-bit value. This patch includes support on mesa glsl and nir. --- src/compiler/glsl_types.h | 24 src/compiler/nir/nir_gather_info.c | 23 --- src/compiler/ni

[Mesa-dev] [PATCH 30/45] i965/fs: Use byte scattered read

From: Jose Maria Casanova Crespo Added on do_untyped_vector_read, that is used on the following intrinsics: * nir_intrinsic_load_shared * nir_intrinsic_load_ubo * nir_intrinsic_load_ssbo --- src/intel/compiler/brw_fs_nir.cpp | 27 +++ 1 file changed, 23 insertion

[Mesa-dev] [PATCH 32/45] i965/compiler: includes 16-bit vertex input

From: Jose Maria Casanova Crespo Includes the info about 16-bit vertex inputs coming from nir on brw VS prog data, as we already do with 64-bit vertex input. --- src/intel/compiler/brw_compiler.h | 1 + src/intel/compiler/brw_vec4.cpp | 1 + 2 files changed, 2 insertions(+) diff --git a/src/i

[Mesa-dev] [PATCH 33/45] anv/pipeline: Use 32-bit surface formats for 16-bit formats

From Vulkan 1.0.50 spec, Section 3.30.1. Format Definition: VK_FORMAT_R16G16_SFLOAT A two-component, 32-bit signed floating-point format that has a 16-bit R component in bytes 0..1, and a 16-bit G component in bytes 2..3. So this format expects those 16-bit floats to be passed wit

[Mesa-dev] [PATCH 34/45] anv/cmd_buffer: Add a padding to the vertex buffer

As we are using 32-bit surface formats with 16-bit elements we can be on a situation where a vertex element can poke over the buffer by 2 bytes. To avoid that we add a padding when flushing the state. This is similar to what the i965 drivers prior to Haswell do, as they use 4-component formats to

[Mesa-dev] [PATCH 35/45] i965/fs: Unpack 16-bit from 32-bit components in VS load_input

From: Jose Maria Casanova Crespo The VS load input for 16-bit values receives pairs of 16-bit values packed in 32-bit values. Because of the adjusted format used at: anv/pipeline: Use 32-bit surface formats for 16-bit formats --- src/intel/compiler/brw_fs_nir.cpp | 29 +

[Mesa-dev] [PATCH 36/45] i965/fs: Enable Render Target Write for 16-bit outputs

From: Jose Maria Casanova Crespo Broadwell doesn't support half precisions data formats on render target writes (RTW) messages. So the solution to write 16-bit outputs is to use the conversion from 32-bit to 16-bit when writing 32-bit values on a 16-bit format surface using formats like R16_FLOAT

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