On Fri, Apr 29, 2016 at 01:29:15PM +0200, Samuel Iglesias Gons?lvez wrote:
> From: Iago Toral Quiroga
>
> ---
> src/mesa/drivers/dri/i965/brw_shader.cpp | 28 ++--
> 1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cp
On Mon, May 02, 2016 at 10:02:50AM +0300, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:15PM +0200, Samuel Iglesias Gons?lvez wrote:
> > From: Iago Toral Quiroga
> >
> > ---
> > src/mesa/drivers/dri/i965/brw_shader.cpp | 28 ++--
> > 1 file changed, 22 insertio
On Fri, Apr 29, 2016 at 01:29:20PM +0200, Samuel Iglesias Gons?lvez wrote:
> From: Connor Abbott
>
> v2 (Iago):
> - Squashed bits from 'support double precission constant operands for
> the implementation of 64-bit emit_load_const'.
> - Do not use BRW_REGISTER_TYPE_D for all 32-bit regist
On Sat, 2016-04-30 at 00:50 -0700, Kenneth Graunke wrote:
> On Friday, April 29, 2016 1:29:26 PM PDT Samuel Iglesias Gonsálvez wrote:
> > From: Connor Abbott
> >
> > ---
> > src/mesa/drivers/dri/i965/Makefile.sources | 1 +
> > src/mesa/drivers/dri/i965/brw_fs.cpp| 5 +++
> >
https://bugs.freedesktop.org/show_bug.cgi?id=93551
--- Comment #18 from Ernst Sjöstrand ---
Jamey: I have had your patch applied the whole time, now I tested with you
patch + Karol's patches. It seems highly unlikely to me that the game would
have any chance of working without ARB_shading_languag
On Fri, Apr 29, 2016 at 01:29:23PM +0200, Samuel Iglesias Gons?lvez wrote:
> From: Connor Abbott
>
> v2 (Sam):
> - Add bitsize to brw_type_for_nir_type() in optimize_extract_to_float()
> ---
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12 +---
> 1 file changed, 9 insertions(+), 3 deleti
On Mon, 2016-05-02 at 10:08 +0300, Pohjolainen, Topi wrote:
> On Mon, May 02, 2016 at 10:02:50AM +0300, Pohjolainen, Topi wrote:
> > On Fri, Apr 29, 2016 at 01:29:15PM +0200, Samuel Iglesias Gons?lvez wrote:
> > > From: Iago Toral Quiroga
> > >
> > > ---
> > > src/mesa/drivers/dri/i965/brw_shade
On Fri, Apr 29, 2016 at 01:29:24PM +0200, Samuel Iglesias Gons?lvez wrote:
> From: Connor Abbott
>
> Similar to retype() and offset().
> ---
> src/mesa/drivers/dri/i965/brw_ir_fs.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h
> b/src/me
On Sun, 2016-05-01 at 20:04 -0700, Jordan Justen wrote:
> On 2016-04-29 04:29:56, Samuel Iglesias Gonsálvez wrote:
> > In that case, the writes need two times the size of a 32-bit value.
> > We need to adjust the exec_size, so it is not breaking any hardware
> > rule.
> >
> > Signed-off-by: Samuel
On Mon, May 02, 2016 at 09:22:49AM +0200, Iago Toral wrote:
> On Mon, 2016-05-02 at 10:08 +0300, Pohjolainen, Topi wrote:
> > On Mon, May 02, 2016 at 10:02:50AM +0300, Pohjolainen, Topi wrote:
> > > On Fri, Apr 29, 2016 at 01:29:15PM +0200, Samuel Iglesias Gons?lvez wrote:
> > > > From: Iago Toral
On Mon, 2016-05-02 at 10:34 +0300, Pohjolainen, Topi wrote:
> On Mon, May 02, 2016 at 09:22:49AM +0200, Iago Toral wrote:
> > On Mon, 2016-05-02 at 10:08 +0300, Pohjolainen, Topi wrote:
> > > On Mon, May 02, 2016 at 10:02:50AM +0300, Pohjolainen, Topi wrote:
> > > > On Fri, Apr 29, 2016 at 01:29:15
On Mon, May 02, 2016 at 09:42:14AM +0200, Iago Toral wrote:
> On Mon, 2016-05-02 at 10:34 +0300, Pohjolainen, Topi wrote:
> > On Mon, May 02, 2016 at 09:22:49AM +0200, Iago Toral wrote:
> > > On Mon, 2016-05-02 at 10:08 +0300, Pohjolainen, Topi wrote:
> > > > On Mon, May 02, 2016 at 10:02:50AM +030
On Mon, 2016-05-02 at 10:54 +0300, Pohjolainen, Topi wrote:
> On Mon, May 02, 2016 at 09:42:14AM +0200, Iago Toral wrote:
> > On Mon, 2016-05-02 at 10:34 +0300, Pohjolainen, Topi wrote:
> > > On Mon, May 02, 2016 at 09:22:49AM +0200, Iago Toral wrote:
> > > > On Mon, 2016-05-02 at 10:08 +0300, Pohj
On Fri, Apr 29, 2016 at 01:29:27PM +0200, Samuel Iglesias Gons?lvez wrote:
> From: Connor Abbott
>
> ---
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_
On Fri, Apr 29, 2016 at 01:29:28PM +0200, Samuel Iglesias Gons?lvez wrote:
> From: Iago Toral Quiroga
>
> When we are actually creating a double using values obtained from a
> previous unpack operation we can bypass the unpack and source from
> the original double value directly.
> ---
> src/mes
On Fri, Apr 29, 2016 at 01:29:29PM +0200, Samuel Iglesias Gons?lvez wrote:
> From: Iago Toral Quiroga
>
> When we are actually unpacking from a double that we have previously
> packed from its 32-bit components we can bypass the pack operation
> and source from its arguments directly.
> ---
> sr
On Fri, Apr 29, 2016 at 01:29:40PM +0200, Samuel Iglesias Gons?lvez wrote:
> From: Connor Abbott
>
> ---
> src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
> b/src/mesa/drivers/dri/i965/br
On May 1, 2016 11:24 PM, "Jonathan Gray" wrote:
>
> % pattern rules are a GNU extension. Convert the use of one to a
> suffix rule to allow this to build on OpenBSD.
>
> Signed-off-by: Jonathan Gray
> ---
> src/intel/genxml/Makefile.am | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
On Mon, May 02, 2016 at 02:23:46AM -0700, Jason Ekstrand wrote:
> On May 1, 2016 11:24 PM, "Jonathan Gray" wrote:
> >
> > % pattern rules are a GNU extension. Convert the use of one to a
> > suffix rule to allow this to build on OpenBSD.
> >
> > Signed-off-by: Jonathan Gray
> > ---
> > src/inte
On May 2, 2016 12:31 AM, "Iago Toral" wrote:
>
> On Sun, 2016-05-01 at 20:04 -0700, Jordan Justen wrote:
> > On 2016-04-29 04:29:56, Samuel Iglesias Gonsálvez wrote:
> > > In that case, the writes need two times the size of a 32-bit value.
> > > We need to adjust the exec_size, so it is not breaki
On Mon, May 2, 2016 at 2:15 AM, Michel Dänzer wrote:
> On 25.04.2016 21:36, Daniel Stone wrote:
>> On 20 April 2016 at 00:32, Rob Clark wrote:
>>> On Tue, Apr 19, 2016 at 7:04 PM, Matt Turner wrote:
Let's let people add themselves to the file if they want. No point in
trying to populat
Hi,
On 2 May 2016 at 11:44, Rob Clark wrote:
> On Mon, May 2, 2016 at 2:15 AM, Michel Dänzer wrote:
>> So, what is this based on? Maybe I'm not looking in the right place, but
>> out of hundreds of changes in Git touching those files, I see one change
>> from you about six months ago and five ch
On Fri, Apr 29, 2016 at 01:29:55PM +0200, Samuel Iglesias Gons?lvez wrote:
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> b/src/me
On Sun, May 01, 2016 at 07:42:42PM -0700, Jordan Justen wrote:
> On 2016-04-29 04:29:53, Samuel Iglesias Gonsálvez wrote:
> > When there is a mix of definitions of uniforms with 32-bit or 64-bit
> > data type sizes, the driver ends up doing misaligned access to double
> > based variables in the pus
On Fri, Apr 29, 2016 at 01:29:53PM +0200, Samuel Iglesias Gons?lvez wrote:
> When there is a mix of definitions of uniforms with 32-bit or 64-bit
> data type sizes, the driver ends up doing misaligned access to double
> based variables in the push constant buffer.
>
> To fix this, the driver adds
On Mon, May 02, 2016 at 04:28:18PM +0300, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:53PM +0200, Samuel Iglesias Gons?lvez wrote:
> > When there is a mix of definitions of uniforms with 32-bit or 64-bit
> > data type sizes, the driver ends up doing misaligned access to double
> > base
On Mon, 2016-05-02 at 10:30 +0300, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:24PM +0200, Samuel Iglesias Gons?lvez wrote:
> > From: Connor Abbott
> >
> > Similar to retype() and offset().
> > ---
> > src/mesa/drivers/dri/i965/brw_ir_fs.h | 8
> > 1 file changed, 8 inserti
Samuel Iglesias Gonsálvez writes:
> Lower lrp when operating with double operands because float version of
> lrp is also lowered.
Kind of silly since there will never be double operands on vc4. I'd
drop the patch, but if you'd like it for consistency:
Acked-by: Eric Anholt
signature.asc
Des
Reviewed-by: Nicolai Hähnle
On 01.05.2016 08:33, Marek Olšák wrote:
From: Marek Olšák
This allows resolving RGBA into RGBX.
This should improve HL2 Lost Coast performance.
---
src/gallium/drivers/radeonsi/si_blit.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/g
For the series:
Reviewed-by: Nicolai Hähnle
On 01.05.2016 08:35, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_debug.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
index
Reviewed-by: Nicolai Hähnle
On 01.05.2016 08:35, Marek Olšák wrote:
From: Marek Olšák
This fixes getteximage-depth piglit failures on radeonsi.
Cc: 11.1 11.2
---
src/mesa/state_tracker/st_cb_texture.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/state_tr
Patches 2-10:
Reviewed-by: Nicolai Hähnle
On 01.05.2016 08:51, Marek Olšák wrote:
Hi,
This series drops SI support for kernels < 3.10, and CIK support for kernels <
3.13.
All code that tries to guess tile mode parameters is removed. Everything is
changed to use the tile mode arrays.
There
Reviewed-by: Nicolai Hähnle
On 02.05.2016 00:15, Jan Vesely wrote:
From: Jan Vesely
Signed-off-by: Jan Vesely
---
src/gallium/auxiliary/util/u_blitter.c| 10 +-
src/gallium/auxiliary/util/u_cpu_detect.c | 2 +-
src/gallium/auxiliary/util/u_format.c | 4 ++--
On 05/01/2016 11:58 PM, Daniel Vetter wrote:
Adding Greg Hackmann from the Android side. Greg, please add anyone
else who might be relevant.
On Sat, Apr 30, 2016 at 2:54 PM, Rob Clark wrote:
On Sat, Apr 30, 2016 at 8:26 AM, Marek Olšák wrote:
On Sat, Apr 30, 2016 at 1:55 PM, Rob Clark wrote
https://bugs.freedesktop.org/show_bug.cgi?id=95215
--- Comment #9 from farmboy0+freedesk...@googlemail.com ---
(In reply to Kenneth Graunke from comment #8)
> FWIW, I would prefer not to implement ARB_shading_language_include.
Why not?
--
You are receiving this mail because:
You are the QA Cont
On Mon, May 2, 2016 at 2:27 AM, Jonathan Gray wrote:
> On Mon, May 02, 2016 at 02:23:46AM -0700, Jason Ekstrand wrote:
> > On May 1, 2016 11:24 PM, "Jonathan Gray" wrote:
> > >
> > > % pattern rules are a GNU extension. Convert the use of one to a
> > > suffix rule to allow this to build on Ope
This is for the non-zero-copy case.. for example pixels live in gl
texture in host (vmwgfx/virtgl), or in vram for discrete gpu perhaps
(or some tiled format, etc).
Since in those cases, you have to copy part of the buffer, as
specified by the bounding box, to and/or from staging buffer (based on
On Fri, Apr 29, 2016 at 7:29 AM, Samuel Iglesias Gonsálvez
wrote:
> From: Iago Toral Quiroga
>
> When we are actually creating a double using values obtained from a
> previous unpack operation we can bypass the unpack and source from
> the original double value directly.
> ---
> src/mesa/drivers
Same comment about missing the check for a non-SSA source.
On Fri, Apr 29, 2016 at 7:29 AM, Samuel Iglesias Gonsálvez
wrote:
> From: Iago Toral Quiroga
>
> When we are actually unpacking from a double that we have previously
> packed from its 32-bit components we can bypass the pack operation
>
On Mon, May 2, 2016 at 9:05 PM, Rob Clark wrote:
> This is for the non-zero-copy case.. for example pixels live in gl
> texture in host (vmwgfx/virtgl), or in vram for discrete gpu perhaps
> (or some tiled format, etc).
>
> Since in those cases, you have to copy part of the buffer, as
> specified
On Mon, May 2, 2016 at 3:21 PM, Marek Olšák wrote:
> On Mon, May 2, 2016 at 9:05 PM, Rob Clark wrote:
>> This is for the non-zero-copy case.. for example pixels live in gl
>> texture in host (vmwgfx/virtgl), or in vram for discrete gpu perhaps
>> (or some tiled format, etc).
>>
>> Since in those
This makes more sense for them.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_qu
This will allow to use percentages for some metrics because the Gallium
HUD doesn't allow to display floating point numbers and 0 is printed
instead.
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/nvc0/nvc0_query_hw_metric.c| 40 --
1 file changed, 22 insertions(+
This is most likely a copy-paste error when I reworked this area few
weeks ago. For SM20, metric-issue_slots is equal to inst_issued because
there is only one pipeline, so the metric is not exposed there.
Signed-off-by: Samuel Pitoiset
Reported-by: Karol Herbst
---
.../drivers/nouveau/nvc0/nvc0
metric-issue_slot_utilization and metric-branch_efficiency are already
computed as percentages.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/
On Mon, May 2, 2016 at 9:51 PM, Rob Clark wrote:
> On Mon, May 2, 2016 at 3:21 PM, Marek Olšák wrote:
>> On Mon, May 2, 2016 at 9:05 PM, Rob Clark wrote:
>>> This is for the non-zero-copy case.. for example pixels live in gl
>>> texture in host (vmwgfx/virtgl), or in vram for discrete gpu perha
Reviewed-by: Jakob Sinclair
On 2016-05-02 07:15, Jan Vesely wrote:
From: Jan Vesely
Signed-off-by: Jan Vesely
---
src/gallium/auxiliary/util/u_blitter.c| 10 +-
src/gallium/auxiliary/util/u_cpu_detect.c | 2 +-
src/gallium/auxiliary/util/u_format.c | 4 ++--
sr
From: Nicolai Hähnle
This tells LLVM to always use SMEM loads for descriptors. It fixes a
regression in piglit's
arb_shader_storage_buffer_object/execution/indirect.shader_test
that was caused by LLVM r268259 (but the proper fix is really here in Mesa).
---
src/gallium/drivers/radeonsi/si_shade
On Monday, May 2, 2016 9:15:53 AM PDT Iago Toral wrote:
> On Sat, 2016-04-30 at 00:50 -0700, Kenneth Graunke wrote:
> > On Friday, April 29, 2016 1:29:26 PM PDT Samuel Iglesias Gonsálvez wrote:
> > > From: Connor Abbott
> > >
> > > ---
> > > src/mesa/drivers/dri/i965/Makefile.sources | 1 +
Samuel Iglesias Gonsálvez writes:
> Hello,
>
> This patch series continues adding arb_gpu_shader_fp64 support to the
> Intel driver. Specifically, this targets the i965 scalar backend for
> BDW+ hardware (vec4 is still under research and gen7 has its own
> issues which we intend tackle after gen
I neglected to include a cpu test in my list of regressions:
piglit.spec.glsl-1_10.compiler.vector-dereference-in-dereference.frag
asserts with "glslparsertest:
src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp:422: virtual
ir_visitor_status
ir_channel_expressions_visitor::visit_le
On 2016-05-01 22:47:40, Jordan Justen wrote:
> 7-10, 12-20, 36-43, 57-58:
> Reviewed-by: Jordan Justen
34-35 Reviewed-by: Jordan Justen
>
> I also sent questions about 56 & 59.
>
> On 2016-04-29 04:28:57, Samuel Iglesias Gonsálvez wrote:
> > Hello,
> >
> > This patch series continues adding
On Friday, April 29, 2016 1:29:53 PM PDT Samuel Iglesias Gonsálvez wrote:
> When there is a mix of definitions of uniforms with 32-bit or 64-bit
> data type sizes, the driver ends up doing misaligned access to double
> based variables in the push constant buffer.
>
> To fix this, the driver adds p
On Monday, May 2, 2016 4:10:38 PM PDT Kenneth Graunke wrote:
> The idea of "upload all the 64-bit things first, add 0 or 1 padding
> slots, then upload all the 32-bit things" also seems like it could
> simplify this code a lot.
Sorry, I misspoke - if you upload all the 64-bit things first, then
yo
On 2016-05-02 00:31:41, Iago Toral wrote:
> On Sun, 2016-05-01 at 20:04 -0700, Jordan Justen wrote:
> > On 2016-04-29 04:29:56, Samuel Iglesias Gonsálvez wrote:
> > > In that case, the writes need two times the size of a 32-bit value.
> > > We need to adjust the exec_size, so it is not breaking any
---
src/gallium/drivers/i915/i915_fpc_translate.c| 4 ++--
src/gallium/drivers/i915/i915_resource_texture.c | 4 ++--
src/gallium/drivers/i915/i915_state.c| 8
src/gallium/drivers/i915/i915_state_dynamic.c| 2 +-
src/gallium/drivers/i915/i915_state_emit.c | 4 ++-
If, for example, we previously had 2 sampler states bound and now we
are binding one, we'd leave the second sampler state unchanged.
This change nulls-out the second sampler state in this situation.
We're already doing the same thing for sampler views.
This silences an occasional warning issued by
---
src/gallium/drivers/ilo/ilo_blit.h| 2 +-
src/gallium/drivers/ilo/ilo_render.c | 2 +-
src/gallium/drivers/ilo/ilo_render_dynamic.c | 8
src/gallium/drivers/ilo/ilo_render_surface.c | 4 ++--
src/gallium/drivers/ilo/ilo_screen.c
---
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index b8b9e4a..7007d20 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdli
---
src/gallium/drivers/trace/tr_dump_state.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/trace/tr_dump_state.c
b/src/gallium/drivers/trace/tr_dump_state.c
index 591ca79..bc129e0 100644
--- a/src/gallium/drivers/trace/tr_dump_state.c
+++ b/src/g
---
src/gallium/drivers/rbug/rbug_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/rbug/rbug_context.c
b/src/gallium/drivers/rbug/rbug_context.c
index 38dee74..54564c1 100644
--- a/src/gallium/drivers/rbug/rbug_context.c
+++ b/src/gallium/drivers/r
Silences warnings from -Wpedantic:
In file included from ../../src/compiler/glsl/glsl_symbol_table.h:34:0,
from ../../src/compiler/glsl/glsl_parser_extras.h:35,
from nir/glsl_to_nir.h:29,
from nir/glsl_to_nir.cpp:51:
../../src/compiler/glsl/ir.h:37
On Mon, May 2, 2016 at 8:02 PM, Brian Paul wrote:
>
Reviewed-by: Rob Clark
> ---
> src/gallium/drivers/freedreno/ir3/ir3_cmdline.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
> b/src/gallium/drivers/freedreno/ir3/ir3
On Mon, May 2, 2016 at 8:02 PM, Brian Paul wrote:
> If, for example, we previously had 2 sampler states bound and now we
> are binding one, we'd leave the second sampler state unchanged.
> This change nulls-out the second sampler state in this situation.
> We're already doing the same thing for sa
I know I've been sticking commas at the end of enums left and right
for the past several years, and haven't heard any complaints. The nice
thing about the trailing comma is that you avoid having to change
unrelated lines when adding entries. This leads to cleaner per-line
histories, which can be us
On Sun, May 1, 2016 at 6:42 AM, Emil Velikov wrote:
> The DRI flush extension should already do the same thing.
>
> Cc: Rob Herring
> Signed-off-by: Emil Velikov
> ---
> NOTE: Untested, although based on my humble understanding of things it
> should be fine.
Seems to work fine with virgl.
Test
On Mon, May 02, 2016 at 11:44:35AM -0700, Jason Ekstrand wrote:
> On Mon, May 2, 2016 at 2:27 AM, Jonathan Gray wrote:
>
> > On Mon, May 02, 2016 at 02:23:46AM -0700, Jason Ekstrand wrote:
> > > On May 1, 2016 11:24 PM, "Jonathan Gray" wrote:
> > > >
> > > > % pattern rules are a GNU extension.
On 05/02/2016 06:15 PM, Ilia Mirkin wrote:
I know I've been sticking commas at the end of enums left and right
for the past several years, and haven't heard any complaints. The nice
thing about the trailing comma is that you avoid having to change
unrelated lines when adding entries. This leads t
Silences warnings with 32-bit Linux gcc builds and MinGW which doesn't
recognize the ‘t’ conversion character.
---
src/mesa/main/bufferobj.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 731b62e..e60a8ea 1
Samuel Iglesias Gonsálvez writes:
> From: Connor Abbott
>
> Similar to retype() and offset().
> ---
> src/mesa/drivers/dri/i965/brw_ir_fs.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h
> b/src/mesa/drivers/dri/i965/brw_ir_fs.h
> index e
With classic DRI drivers, the DRI Configuration Infrastructure can be used
to read driver-specific parameters from XML files. The i965 driver
(src/mesa/drivers/dri/i965/intel_screen.c) uses this feature for instance.
In Gallium, the DRI Configuration Infrastructure is used to set common
options (
https://bugs.freedesktop.org/show_bug.cgi?id=95246
Bug ID: 95246
Summary: Segfault in glBindFramebuffer()
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NEW
Severity: normal
Priority:
https://bugs.freedesktop.org/show_bug.cgi?id=95246
--- Comment #1 from Daniel Scharrer ---
Backtrace:
#0 driver_RenderTexture_is_safe (att=att@entry=0xb33570)
at
/var/tmp/portage/media-libs/mesa-/work/mesa-/src/mesa/main/fbobject.c:392
#1 0x729aabc3 in check_begin_texture_r
Samuel Iglesias Gonsálvez writes:
> Hello,
>
> This patch series continues adding arb_gpu_shader_fp64 support to the
> Intel driver. Specifically, this targets the i965 scalar backend for
> BDW+ hardware (vec4 is still under research and gen7 has its own
> issues which we intend tackle after gen
From: Dave Airlie
This fixes a crash in
GL43-CTS.shader_subroutine.subroutines_not_allowed_as_variables_constructors_and_argument_or_return_types
Signed-off-by: Dave Airlie
---
src/compiler/glsl/ast_function.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/compil
From: Dave Airlie
This fixes two of the cases in
GL43-CTS.shader_subroutine.subroutines_not_allowed_as_variables_constructors_and_argument_or_return_types
Signed-off-by: Dave Airlie
---
src/compiler/glsl/ast_function.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/compiler/gl
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On 29/04/16 20:43, Jason Ekstrand wrote:
> Why not just squash 2 and 3 and call it "Separate 32 and 64-bit
> fmod lowering" or something like that.
>
OK, I like it.
Sam
>
> On Thu, Apr 28, 2016 at 4:19 AM, Samuel Iglesias Gonsálvez <
> sigles
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On 29/04/16 20:26, Jordan Justen wrote:
> On 2016-04-28 04:19:18, Samuel Iglesias Gonsálvez wrote:
>> Make this distintion as the drivers might need to lower it inside NIR
.
>>
>> Signed-off-by: Samuel Iglesias Gonsálvez
>> ---
>> src/compiler/ni
From: Dave Airlie
GL43-CTS.texture_view.errors checks for GL_INVALID_VALUE
here but we catch these problems in the dimensionsOK check
and return the wrong error value.
This fixes:
GL43-CTS.texture_view.errors.
Signed-off-by: Dave Airlie
---
src/mesa/main/textureview.c | 50 +++
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On 30/04/16 09:20, Kenneth Graunke wrote:
> On Friday, April 29, 2016 1:29:19 PM PDT Samuel Iglesias Gonsálvez
> wrote:
>> From: Connor Abbott
>>
>> --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +++ 1 file changed,
>> 3 insertions(+)
>>
>> diff -
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On 30/04/16 09:26, Kenneth Graunke wrote:
> On Friday, April 29, 2016 1:29:20 PM PDT Samuel Iglesias Gonsálvez
> wrote:
>> From: Connor Abbott
>>
>> v2 (Iago): - Squashed bits from 'support double precission
>> constant operands for the implement
From: Dave Airlie
This fixes
GL43-CTS.copy_image.samples_missmatch
which otherwise asserts in the radeonsi driver.
Signed-off-by: Dave Airlie
---
src/mesa/main/copyimage.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/main/copyimage.c b/src/mesa/main/copyimage.c
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On 29/04/16 18:44, Connor Abbott wrote:
> IIRC this is wrong. I think I added it in the beginning before I
> tested to see if the spec was lying about math instructions not
> being supported on doubles (it wasn't) and we can delete it now
> that w
Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on
Gen >= 8 platforms. This patch avoids the GPU hangs, but does not
implement a full work around for the restriction (dispatch_width == 16
is an imperfect proxy).
Evidently that commit allowed the scheduler to make different cho
AGP mode is unstable on PowerPC
---
drivers/gpu/drm/radeon/radeon_drv.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index ccd4ad4..d1cfccf 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/
On Mon, 2016-05-02 at 14:40 -0700, Kenneth Graunke wrote:
> On Monday, May 2, 2016 9:15:53 AM PDT Iago Toral wrote:
> > On Sat, 2016-04-30 at 00:50 -0700, Kenneth Graunke wrote:
> > > On Friday, April 29, 2016 1:29:26 PM PDT Samuel Iglesias Gonsálvez wrote:
> > > > From: Connor Abbott
> > > >
> >
On Mon, May 02, 2016 at 11:32:13PM -0700, Matt Turner wrote:
> Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on
> Gen >= 8 platforms. This patch avoids the GPU hangs, but does not
> implement a full work around for the restriction (dispatch_width == 16
> is an imperfect proxy
Dear all,
I've tested a patch against radeon_drc.c so that the default mode is
now PCI on PowerPC arch.
This is the result of the discussion on the following bug report:
https://bugs.freedesktop.org/show_bug.cgi?id=95017
I had prepared a less invasive patch (targetting only the specific
subsyst
From: Dave Airlie
resource just appears in GLSL 4.20 without any fanfare.
Fixes GL43-CTX.CommonBugs.CommonBug_ReservedNames
Signed-off-by: Dave Airlie
---
src/compiler/glsl/glsl_lexer.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/glsl/glsl_lexer.ll b/src/
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On 02/05/16 07:47, Jordan Justen wrote:
> 7-10, 12-20, 36-43, 57-58: Reviewed-by: Jordan Justen
>
>
> I also sent questions about 56 & 59.
>
Thanks a lot for your reviews!
I am still catching up email and doing the required changes to each
pat
On 02/05/16 08:24, Pohjolainen, Topi wrote:
> On Fri, Apr 29, 2016 at 01:29:12PM +0200, Samuel Iglesias Gons?lvez wrote:
>> From: Connor Abbott
>>
>> ---
>> src/mesa/drivers/dri/i965/brw_eu_emit.c | 28 +---
>> 1 file changed, 21 insertions(+), 7 deletions(-)
>>
>> diff
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