Signed-off-by: Juha-Pekka Heikkila
---
src/glx/glxcmds.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/src/glx/glxcmds.c b/src/glx/glxcmds.c
index b5377c2..38a5262 100644
--- a/src/glx/glxcmds.c
+++ b/src/glx/glxcmds.c
@@ -385,7 +385,9 @@ glXCre
Signed-off-by: Juha-Pekka Heikkila
---
src/glx/glxext.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/glx/glxext.c b/src/glx/glxext.c
index 2711e57..4a195bd 100644
--- a/src/glx/glxext.c
+++ b/src/glx/glxext.c
@@ -269,7 +269,8 @@ __glXCloseDisplay(Display * dpy, XExtCo
https://bugs.freedesktop.org/show_bug.cgi?id=72926
Alexander Monakov changed:
What|Removed |Added
CC||amona...@gmail.com
--- Comment #1 fr
https://bugs.freedesktop.org/show_bug.cgi?id=72926
--- Comment #2 from Peter Wu ---
Created attachment 91216
--> https://bugs.freedesktop.org/attachment.cgi?id=91216&action=edit
api trace output (gzipped)
Java has no love for valgrind, it hits the 10 million error count before a
window even ge
Hello,
I have an application that on each frame fills a full-window pixel buffer
and then calls glTexSubImage2D() and maps the texture to a screen by
drawing full-window rectangle (my hardware is Intel(R) Core(TM) i7-2670QM
CPU @ 2.20GHz (brw->gen == 6), OpenGL 3.0, direct glDrawPixels() is much
s
2013/12/27 Tomash Brechko
> By forcing intel_region_alloc() to use I915_TILING_X I get 50% FPS rise
> (for glxgears 2400FPS -> 3600FPS in default window, 108FPS -> 175FPS for
> 1920x1080 fullscreen).
>
To clarify the statement about glxgears: of cource it doesn't use
glTexSubImage2D() itself, I
Reviewed-by: Marek Olšák
Marek
On Thu, Dec 26, 2013 at 7:06 PM, Christoph Bumiller
wrote:
> ---
> src/mesa/state_tracker/st_extensions.c | 4 +++-
> src/mesa/state_tracker/st_format.c | 6 +-
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_
From: Marek Olšák
---
src/mesa/state_tracker/st_cb_clear.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_clear.c
b/src/mesa/state_tracker/st_cb_clear.c
index 363f2f7..a84c907 100644
--- a/src/mesa/state_tracker/st_cb_clear.c
From: Marek Olšák
v2: clear depth and stencil together
---
src/mesa/state_tracker/st_cb_clear.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_clear.c
b/src/mesa/state_tracker/st_cb_clear.c
index 887e58b..363f2f7 100644
---
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_state.c | 33 ---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 5
src/gallium/winsys/radeon/drm/radeon_winsys.h | 3 +++
3 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/src/gall
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_texture.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index c7ef277..caf3743 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/
Okay. Using Axxx for transfers only is a good idea, just please make
sure the formats are not advertised to the state tracker.
Also, resource_copy_region doesn't (it sometimes does, but shouldn't)
do format conversions, so pipe->blit must be used instead. You can
fork r600_copy_region_with_blit fo
Hi,
i965 texture fast upload path did not work in 9.2.x due to this tiling
change, but was improved for 10.0 release series; however, you need to
use GL_UNSIGNED_BYTE format rather than GL_UNSIGNED_INT_8_8_8_8_REV to
hit it. With that, upload on 10.0.x should be almost as fast as on
9.1.x. Funny
On 12/27/2013 05:56 AM, Tomash Brechko wrote:
> So I wonder if there are strong reasons to prefer Y tiling for textures,
> at least on gen == 6? Is Y tiling preffered because of faster texel
> lookups (assuming glTexSubImage2D() is not called on each frame)?
Yes, I observed an ~8% improvement in
On 12/24/2013 03:47 PM, Eric Anholt wrote:
> We definitely want to fall through to the unsynchronized map case, instead
> of wasting bandwidth on a copy. Prevents a -43.2407% +/- 1.06113% (n=49)
> performance regression on aa10perf when teaching glamor to provide the
> GL_INVALIDATE_RANGE_BIT info
Marek Olšák writes:
> Some of the code seems to be copy-pasted from
> dri2_drawable_process_buffers. The MSAA color and depth-stencil
> texture allocation could be moved to a common function.
It's either that or plan on moving DRI2 to the image interface as well
at some point? As we'll have to k
I'm not sure if this is relevant to the i965 fs backend in particular, but
Briggs in his thesis [1] recommended simply ignoring the liveness of any
register read by a copy instruction immediately after said instruction when
computing the interference graph in order to solve this exact problem (see
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