Am 02.11.2015 um 22:39 schrieb Dave Airlie:
> On 3 November 2015 at 07:31, Roland Scheidegger wrote:
>> Am 02.11.2015 um 20:55 schrieb Ilia Mirkin:
>>> FTR these are the various operators on nvidia hw:
>>>
>>> https://urldefense.proofpoint.com/v2/url?u=http-3A__docs.nvidia.com_cuda_parallel-2Dthre
On 3 November 2015 at 07:31, Roland Scheidegger wrote:
> Am 02.11.2015 um 20:55 schrieb Ilia Mirkin:
>> FTR these are the various operators on nvidia hw:
>>
>> https://urldefense.proofpoint.com/v2/url?u=http-3A__docs.nvidia.com_cuda_parallel-2Dthread-2Dexecution_-23cache-2Doperators&d=BQIFaQ&c=Sqc
Am 02.11.2015 um 20:55 schrieb Ilia Mirkin:
> FTR these are the various operators on nvidia hw:
>
> https://urldefense.proofpoint.com/v2/url?u=http-3A__docs.nvidia.com_cuda_parallel-2Dthread-2Dexecution_-23cache-2Doperators&d=BQIFaQ&c=Sqcl0Ez6M0X8aeM67LKIiDJAXVeAw-YihVMNtXt-uEs&r=Vjtt0vs_iqoI31UfJ
On Mon, Nov 2, 2015 at 8:07 PM, Ilia Mirkin wrote:
> I haven't the faintest idea about efficiently, but these things flags
> on the ld/st instructions in the nvidia ISA for SM20+ (and I just
> plain don't know about SM10). I'm moderately sure that's the case for
> GCN as well.
>
> The difficulty w
FTR these are the various operators on nvidia hw:
http://docs.nvidia.com/cuda/parallel-thread-execution/#cache-operators
Most of these map directly to instruction things (ca/cg/cs/cv sound
familiar, dunno about lu, could just be an assembler helper).
How backwards-compatible is TGSI supposed to
Ok, I guess if it's really flagged on the instructions in hw, it seems
reasonable to do it on the instructions in tgsi as well.
Using the last two bits there doesn't sound nice indeed (in particular
if maybe you'd wanted to encode the read/write bits as well at some
point too), but it's not THAT ba
Another fun example to try to express properly in TGSI:
buffer foo {
struct bar {
coherent int a;
int b;
} asdf[10];
}
Now all of a sudden you have to worry about stride for the declarations.
-ilia
On Mon, Nov 2, 2015 at 2:07 PM, Ilia Mirkin wrote:
> I haven't the faintest idea
I haven't the faintest idea about efficiently, but these things flags
on the ld/st instructions in the nvidia ISA for SM20+ (and I just
plain don't know about SM10). I'm moderately sure that's the case for
GCN as well.
The difficulty with TGSI is that you might have something like
layout (std430)
I don't know much about ssbo, but since it looks like in glsl the
coherent etc. bits are on the variables, not the ops, it seems unnatural
to mark the op bits instead. So I'd guess it would be better if the
variables could be marked instead. If this isn't expressible in tgsi
maybe this needs to be
I'm okay with adding flags wherever you want, but please note that if
you add flags to declarations, you may need array support on the
declarations, so that instructions can tell which variable is being
used when indirect addressing is being used. CONSTs don't need array
support because the declara
Just wanted to note down some thoughts and get some feedback before
going forward. I've already sent out a series which covered a lot of
this, but in the end I realized it came up a bit short (available at
https://github.com/imirkin/mesa/commits/fd2).
There are two separate buffer-related features
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