Re: [Mesa-dev] NIR issue with SPIRV ops that have operands with different bit-size

Thanks to all for the opinions. I'm going to implement the conversion then. Sam On 24/04/18 15:45, Jason Ekstrand wrote: > On Tue, Apr 24, 2018 at 6:42 AM, Ian Romanick > wrote: > > On 04/24/2018 05:44 AM, Rob Clark wrote: > > On Tue, Apr 24, 2018 at 4:24 A

Re: [Mesa-dev] NIR issue with SPIRV ops that have operands with different bit-size

Rob Clark writes: > Karol hit the same thing (with for example, shift instructions) with > the work for spv compute/kernel support. I *think* the number of > special cases isn't too high, so probably vtn should just insert the > appropriate conversion instruction (ie. u2u32, etc) so that if the

Re: [Mesa-dev] NIR issue with SPIRV ops that have operands with different bit-size

On Tue, Apr 24, 2018 at 6:42 AM, Ian Romanick wrote: > On 04/24/2018 05:44 AM, Rob Clark wrote: > > On Tue, Apr 24, 2018 at 4:24 AM, Samuel Iglesias Gonsálvez > > wrote: > >> Hello, > >> > >> Recently, we have found problems between some SPIRV opcodes and NIR. > >> > >> SPIR-V allows opcodes to

Re: [Mesa-dev] NIR issue with SPIRV ops that have operands with different bit-size

On 04/24/2018 05:44 AM, Rob Clark wrote: > On Tue, Apr 24, 2018 at 4:24 AM, Samuel Iglesias Gonsálvez > wrote: >> Hello, >> >> Recently, we have found problems between some SPIRV opcodes and NIR. >> >> SPIR-V allows opcodes to mix different bit-sizes for their operands, such as >> for some bitfie

Re: [Mesa-dev] NIR issue with SPIRV ops that have operands with different bit-size

On Tue, Apr 24, 2018 at 4:24 AM, Samuel Iglesias Gonsálvez wrote: > Hello, > > Recently, we have found problems between some SPIRV opcodes and NIR. > > SPIR-V allows opcodes to mix different bit-sizes for their operands, such as > for some bitfield operations and other ops like bitwise shifts. >

[Mesa-dev] NIR issue with SPIRV ops that have operands with different bit-size

Hello, Recently, we have found problems between some SPIRV opcodes and NIR. SPIR-V allows opcodes to mix different bit-sizes for their operands, such as for some bitfield operations and other ops like bitwise shifts. In NIR, when the ALU opcode doesn't have specified bitsizes for their operands