On Tue, Jan 09, 2018 at 11:26:26AM -0800, Jason Ekstrand wrote:
> On Tue, Jan 9, 2018 at 10:33 AM, Nanley Chery wrote:
>
> > On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> > > On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery
> > wrote:
> > >
> > > > On Fri, Dec 15, 2017 at 02:53:3
On Mon, Jan 08, 2018 at 04:33:25PM -0800, Rafael Antognolli wrote:
> On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> > On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery wrote:
> >
> > On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > > On Gen10+, if we us
On Tue, Jan 9, 2018 at 10:33 AM, Nanley Chery wrote:
> On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> > On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery
> wrote:
> >
> > > On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > > > On Gen10+, if we use the clear sta
On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery wrote:
>
> > On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > > On Gen10+, if we use the clear state address field in the surface state
> > > instead of the clear c
On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery wrote:
>
> On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > On Gen10+, if we use the clear state address field in the surface state
> > instead of the c
On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery wrote:
> On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > On Gen10+, if we use the clear state address field in the surface state
> > instead of the clear color directly, there's a restriction that the
> > address must point to th
On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> On Gen10+, if we use the clear state address field in the surface state
> instead of the clear color directly, there's a restriction that the
> address must point to the lower part of a 64 byte cache-line.
>
> Signed-off-by: Rafa
On Gen10+, if we use the clear state address field in the surface state
instead of the clear color directly, there's a restriction that the
address must point to the lower part of a 64 byte cache-line.
Signed-off-by: Rafael Antognolli
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src/intel/vulkan/anv_private.h | 12 +++-
1 file