On Wed, Nov 18, 2015 at 3:09 PM, Ilia Mirkin wrote:
> On Wed, Nov 18, 2015 at 6:06 PM, Matt Turner wrote:
>> In most cases (when the negate is copy propagated and the MOV removed),
>> this is two instructions on Gen >= 8 and only two instructions on
>> earlier platforms -- and it doesn't use the
On Wed, Nov 18, 2015 at 6:06 PM, Matt Turner wrote:
> In most cases (when the negate is copy propagated and the MOV removed),
> this is two instructions on Gen >= 8 and only two instructions on
> earlier platforms -- and it doesn't use the flag register.
> ---
> Thanks Ilia!
>
> src/mesa/drivers/
In most cases (when the negate is copy propagated and the MOV removed),
this is two instructions on Gen >= 8 and only two instructions on
earlier platforms -- and it doesn't use the flag register.
---
Thanks Ilia!
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 52
1 f
On Wed, Nov 18, 2015 at 2:25 PM, Matt Turner wrote:
> ---
> This fails... for reasons I cannot determine. Can anyone spot what's wrong?
Ilia identified the problem in 10 seconds -- I need to NOT the pixel
mask. A set bit in the mask means the channel is enabled, and that's
the opposite of what gl
---
This fails... for reasons I cannot determine. Can anyone spot what's wrong?
I'm okay with just committing the v1 of 2/2 and not blocking this feature on
this optimization.
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 43
1 file changed, 43 insertions(+)
diff -
On Fri, Nov 13, 2015 at 6:05 PM, Matt Turner wrote:
> ---
> This code generates
>
> mov(1) f0<1>UW g1.14<0,1,0>UW
> mov(8) g2<1>UD 0xUD
> (+f0) sel(8)g3<1>D g2<8,8,1>D -1D
>
> which I don't love because it uses the
---
This code generates
mov(1) f0<1>UW g1.14<0,1,0>UW
mov(8) g2<1>UD 0xUD
(+f0) sel(8)g3<1>D g2<8,8,1>D -1D
which I don't love because it uses the flag register, and likely uses
of gl_HelperInvocation will be in a
