On 4 November 2017 at 10:01, Marek Olšák wrote:
> Not sure if the "HW" prefix everywhere makes sense since gallium
> doesn't imply there is a hardware driver behind it, but I don't really
> care much.
Well it's more that the atomic's aren't normal ssbo atomics, and there is
dedicated hardware for
Not sure if the "HW" prefix everywhere makes sense since gallium
doesn't imply there is a hardware driver behind it, but I don't really
care much.
Marek
On Fri, Nov 3, 2017 at 8:24 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This looks like an evergreen specific feature, but with atomic
> co
Am Freitag, den 03.11.2017, 17:24 +1000 schrieb Dave Airlie:
> From: Dave Airlie
>
[...]
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 875aff6..39f7b7b 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/rad
From: Dave Airlie
This looks like an evergreen specific feature, but with atomic
counters AMD have hw specific counters they use instead of operating
on buffers directly. These are separate to the buffer atomics,
so require different limits and code paths.
I've left the CAP for atomic type exten
