On 07/18/2013 12:20 AM, Kenneth Graunke wrote:
On 07/17/2013 04:46 PM, Chad Versace wrote:
+/* Memory Object Control State, Gen7 */
+/* L3 Cacheability Control */
+#define GEN7_MOCS_L3_UNCACHEABLE0
+#define GEN7_MOCS_L3_CACHEABLE 1
+/* LCC Cacheability Control
On 07/17/2013 04:46 PM, Chad Versace wrote:
For Ivybridge and Haswell.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_defines.h | 20
1 file changed, 20 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_de
For Ivybridge and Haswell.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_defines.h | 20
1 file changed, 20 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index fa257ac..ebce8b9 100644
--- a/src/
For Ivybridge and Haswell.
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_defines.h | 20
1 file changed, 20 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index fa257ac..ebce8b9 100644
--- a/src/
On 05/09/2013 04:48 PM, Chad Versace wrote:
Tested-by: Matt Turner
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_defines.h | 20
1 file changed, 20 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_define
Tested-by: Matt Turner
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_defines.h | 20
1 file changed, 20 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 6517f24..f574cb7 100644
--- a/src/mesa
CC: Stéphane Marchesin
CC: Kenneth Graunke
CC: Eric Anholt
CC: Matt Turner
Signed-off-by: Chad Versace
---
src/mesa/drivers/dri/i965/brw_defines.h | 20
1 file changed, 20 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/br