On Tue, Aug 21, 2018 at 2:26 PM Andres Rodriguez wrote:
>
>
>
> On 2018-08-21 01:54 PM, Marek Olšák wrote:
> > Note that WAVES_PER_SH should be 0x3ff on the compute ring for the
> > ring priorities to be applied.
>
> Correct, we would need to set WAVES_PER_SH during pipeline creation.
>
> > I don'
On 2018-08-21 01:54 PM, Marek Olšák wrote:
Note that WAVES_PER_SH should be 0x3ff on the compute ring for the
ring priorities to be applied.
Correct, we would need to set WAVES_PER_SH during pipeline creation.
I don't know if you need to do the same
thing for the gfx ring. You can ask Andre
Note that WAVES_PER_SH should be 0x3ff on the compute ring for the
ring priorities to be applied. I don't know if you need to do the same
thing for the gfx ring. You can ask Andres for more info.
Marek
On Tue, Aug 14, 2018 at 12:10 PM Samuel Pitoiset
wrote:
>
> The last parameter of radeon_set_sh
You are lucky that WAVES_PER_SH was not 3. Such a low limit could
decrease compute shader performance to ~2%.
Marek
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On 8/15/18 3:34 PM, Bas Nieuwenhuizen wrote:
On Wed, Aug 15, 2018 at 2:13 PM, Samuel Pitoiset
wrote:
On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote:
On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset
wrote:
The last parameter of radeon_set_sh_reg_seq() is the number of
dwords to emit. We we
On Wed, Aug 15, 2018 at 2:13 PM, Samuel Pitoiset
wrote:
>
>
> On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote:
>>
>> On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset
>> wrote:
>>>
>>> The last parameter of radeon_set_sh_reg_seq() is the number of
>>> dwords to emit. We were lucky because WAVES_PER_SH
On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote:
On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset
wrote:
The last parameter of radeon_set_sh_reg_seq() is the number of
dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but
it was initialized to 0.
COMPUTE_RESOURCE_LIMITS is correctly s
On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset
wrote:
> The last parameter of radeon_set_sh_reg_seq() is the number of
> dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but
> it was initialized to 0.
>
> COMPUTE_RESOURCE_LIMITS is correctly set when generating
> compute pipelines, s
The last parameter of radeon_set_sh_reg_seq() is the number of
dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but
it was initialized to 0.
COMPUTE_RESOURCE_LIMITS is correctly set when generating
compute pipelines, so we don't need to initialize it.
Signed-off-by: Samuel Pitoiset
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