Re: [Mesa-dev] [PATCH] r600g: pad IBs to a multiple of 4 DWs on r6xx

2013-09-06 Thread Christian König
Actually Type 2 packets are handled much faster on the R6xx compared to most type 3 packets, cause they are handled by the PFP/fetch hw and doesn't need to be forwarded to the ME. Christian. Am 06.09.2013 02:31, schrieb Dominik Behr: 0x8000 is Type 2 NOP. You could make it a little better

Re: [Mesa-dev] [PATCH] r600g: pad IBs to a multiple of 4 DWs on r6xx

2013-09-05 Thread Dominik Behr
0x8000 is Type 2 NOP. You could make it a little better/faster by inserting single multi-DWORD Type 3 NOP And pad to 8 DWORDs. CP fetches are 32 bytes each and R600 has requires padding. Same with padding CP ring buffer updates to 32 bytes (pad to 32bytes before you update CP_RB_WPTR). On Thu

Re: [Mesa-dev] [PATCH] r600g: pad IBs to a multiple of 4 DWs on r6xx

2013-09-05 Thread Dominik Behr
0x8000 is Type 2 NOP. You could make it a little better/faster by inserting single multi-DWORD Type 3 NOP And pad to 8 DWORDs. CP fetches are 32 bytes each and R600 has requires padding. Same with padding CP ring buffer updates to 32 bytes (pad to 32bytes before you update CP_RB_WPTR). On Thu

Re: [Mesa-dev] [PATCH] r600g: pad IBs to a multiple of 4 DWs on r6xx

2013-09-05 Thread Marek Olšák
Reviewed-by: Marek Olšák Though I'm not sure if 0x8000 is correct. Marek On Wed, Sep 4, 2013 at 11:55 PM, Alex Deucher wrote: > IBs need to be a multiple of 4 dwords on r6xx asics > to avoid a hw bug. > > Signed-off-by: Alex Deucher > CC: "9.2" > CC: "9.1" > --- > src/gallium/drivers/r

[Mesa-dev] [PATCH] r600g: pad IBs to a multiple of 4 DWs on r6xx

2013-09-04 Thread Alex Deucher
IBs need to be a multiple of 4 dwords on r6xx asics to avoid a hw bug. Signed-off-by: Alex Deucher CC: "9.2" CC: "9.1" --- src/gallium/drivers/r600/r600_hw_context.c | 13 + 1 file changed, 13 insertions(+) diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/dri