Re: [Mesa-dev] [PATCH] i965/gs: Set force_writemask_all when setting up g0.

2013-10-22 Thread Kenneth Graunke
On 10/22/2013 07:32 PM, Paul Berry wrote: > All geometry shaders begin this instruction: > > mov(1) g0.2<1>:ud 0x0:ud { align1 } > > which sets up GRF0 properly for scratch reads and writes. Since this > instruction has a SIMD size of 1, it will only have an effect if the > first channel is

[Mesa-dev] [PATCH] i965/gs: Set force_writemask_all when setting up g0.

2013-10-22 Thread Paul Berry
All geometry shaders begin this instruction: mov(1) g0.2<1>:ud 0x0:ud { align1 } which sets up GRF0 properly for scratch reads and writes. Since this instruction has a SIMD size of 1, it will only have an effect if the first channel is enabled. In practice, the hardware seems to always disp