Re: [Mesa-dev] [PATCH] i965/gen7: Increase the WM threads to hardware limits.

2012-07-20 Thread Matt Turner
On Thu, Jul 19, 2012 at 1:17 AM, Kenneth Graunke wrote: > With my Sandybridge GT2's register 0x20d0 value of 0x0, bumping the > maximum thread count to 80 also seems to work (Unigine Heaven didn't > tank my system). I haven't done any performance measurements. As a quick data point, the Counter-

Re: [Mesa-dev] [PATCH] i965/gen7: Increase the WM threads to hardware limits.

2012-07-19 Thread Kenneth Graunke
On 07/19/2012 12:35 AM, Eric Anholt wrote: > This thread count is only supposed to be enabled when "WIZ Hashing Disable in > GT_MODE register enabled." I've always been confused whether that means the > bit in the register should be 1 or 0. For my IVB GT2's register 0x7008 value > of 0x0, this ap

[Mesa-dev] [PATCH] i965/gen7: Increase the WM threads to hardware limits.

2012-07-19 Thread Eric Anholt
This thread count is only supposed to be enabled when "WIZ Hashing Disable in GT_MODE register enabled." I've always been confused whether that means the bit in the register should be 1 or 0. For my IVB GT2's register 0x7008 value of 0x0, this appears to work fine. Improves l4d2 performance at 6