Re: [Mesa-dev] Update: UVD status on loongson 3a platform

2013-09-05 Thread cee1
nto user process mapping ? ie do you have > something like Intel PAT or something like MTRR or something else. > > In other word, can you map into process address space a region of > io memory (GPU VRAM in this case) and mark it as uncached so that > none of the access to it goes thr

Re: [Mesa-dev] Update: UVD status on loongson 3a platform

2013-09-05 Thread cee1
gt; >> Cheers, >> Jerome > > Also it might be that you can't do write combining on your platform, > which would be a major drawback as it's assume by radeon userspace. > I would need to check the pcie specification, but write combining is > probably not mandatory

Re: [Mesa-dev] [status][help]pipe-video on Loongson3A(mipsel) platform with r600

2011-08-07 Thread cee1
es High@L5.1 and CABAC eg. > > http://www.andyqos.ukfsn.org/Planet_Earth_From_Pole_to_Pole_1080p_sample.mkv > > Then I see a 3x increase between 1 and 4 threads. Just like you said: 1 thread: 685.104s 4 threads: 219.361s -- Regards, - cee1 _