5ba72 in _gbm_create_device (fd=7) at
> ../src/gbm/main/backend.c:229
> #8 0x77e5bbd2 in gbm_create_device (fd=7) at
> ../src/gbm/main/gbm.c:138
>
>
> Regards,
> Mike
>
> On Mon, Jul 22, 2024 at 10:40 AM Lei Zhou wrote:
>
>> Dear mesa/experts,
>>
&g
depend on "-device virtio-gpu-gl-pci" the capsets of
virgl and virgl2, which is not what we are using.
Any clarification will be highly appreciated!
Lei Zhou
ell as radeon_vcn_enc_1_2.c:215
>
> Thanks,
> Boyuan
>
>
> -Original Message-
> From: mesa-dev On Behalf Of Lei Zhou
> Sent: April 15, 2019 2:24 AM
> To: mesa-dev@lists.freedesktop.org
> Subject: [Mesa-dev] [PATCH] radeon: Fix width align for hevc encode
>
The width alignment for HEVC encoding should be 64 due to hardware
requirement. This will fix conformance_window_flag in SPS.
Signed-off-by: Lei Zhou
---
src/gallium/drivers/radeon/radeon_uvd_enc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon
The width alignment for HEVC encoding should be 64 due to hardware
requirement. This will fix conformance_window_flag in SPS.
v2 (Zhang, Boyuan):
- add marcos to define width alignment for hevc and h264
Signed-off-by: Lei Zhou
---
src/gallium/drivers/radeon/radeon_vcn_enc.c | 4 ++--
src
Before, width is aligned to 16, we get 512x800 when encoding
with 480x800, and conformance_window_flag=0 in sps.
Signed-off-by: Lei Zhou
---
src/gallium/drivers/radeon/radeon_uvd_enc.c | 2 +-
src/gallium/drivers/radeon/radeon_vcn_enc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions
