Re: [Mesa-dev] [PATCH] glapi: Fix DispatchSanity_test

On Fri, Dec 7, 2018 at 3:48 PM Kristian H. Kristensen wrote: > > --- > src/mapi/glapi/gen/EXT_multisampled_render_to_texture.xml | 2 +- > src/mapi/glapi/gen/es_EXT.xml | 2 ++ > src/mapi/glapi/gen/gl_API.xml | 2 -- > src/mesa/main/tests/di

Re: [Mesa-dev] [PATCH 07/20] nir: add guess trip count support to loop analysis

On 8/12/18 11:16 am, Jason Ekstrand wrote: On Thu, Dec 6, 2018 at 9:08 PM Timothy Arceri > wrote: This detects an induction variable used as an array index to guess the trip count of the loop. This enables us to do a partial unroll of the loop, with can

[Mesa-dev] [Bug 94957] dEQP failures on llvmpipe

https://bugs.freedesktop.org/show_bug.cgi?id=94957 --- Comment #13 from Roland Scheidegger --- (In reply to Emil Velikov from comment #12) > The below commit allows us to disable the perf. optimisations (for release > builds), and thus fixing the functional.texture tests. > > Should we close thi

Re: [Mesa-dev] [PATCH] i965: Flip arguments to load_register_reg helpers.

Rb On 08/12/2018 00:32, Kenneth Graunke wrote: load_register_imm and load_register_mem take the destination as the first argument, so I'd like load_register_reg to do the same the sake of consistency. Otherwise, reading sequences of mixed LRI/LRM/LRR is needlessly confusing. --- src/mesa/driv

[Mesa-dev] [PATCH] i965: Flip arguments to load_register_reg helpers.

load_register_imm and load_register_mem take the destination as the first argument, so I'd like load_register_reg to do the same the sake of consistency. Otherwise, reading sequences of mixed LRI/LRM/LRR is needlessly confusing. --- src/mesa/drivers/dri/i965/brw_conditional_render.c | 2 +- src/m

[Mesa-dev] [Bug 108974] make check DispatchSanity_test regression

https://bugs.freedesktop.org/show_bug.cgi?id=108974 Bug ID: 108974 Summary: make check DispatchSanity_test regression Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: All Status: NEW Keywords: bisec

Re: [Mesa-dev] [PATCH 07/20] nir: add guess trip count support to loop analysis

On Thu, Dec 6, 2018 at 9:08 PM Timothy Arceri wrote: > This detects an induction variable used as an array index to guess > the trip count of the loop. This enables us to do a partial > unroll of the loop, with can eventually result in the loop being > eliminated. > --- > src/compiler/nir/nir.h

[Mesa-dev] [RFC PATCH 04/14] anv/allocator: Use anv_state_table on back_alloc too.

--- src/intel/vulkan/anv_allocator.c | 32 ++-- src/intel/vulkan/anv_private.h | 2 +- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c index 5f0458afd77..2171a97970b 100644 --- a/src

[Mesa-dev] [RFC PATCH 07/14] anv: Update usage of block_pool->bo.

Change block_pool->bo to be a pointer, and update its usage everywhere. This makes it simpler to switch it later to a list of BOs. --- src/intel/vulkan/anv_allocator.c | 31 +++--- src/intel/vulkan/anv_batch_chain.c | 8 src/intel/vulkan/anv_blorp.c | 2 +

[Mesa-dev] [RFC PATCH 10/14] anv: Add clflush to states.

TODO: This is just flushing the entire dynamic states on every execbuf. Maybe it's too much. However, in theory we should be already flushing the states as needed, but I think we didn't hit any bug due to the coherence implied by userptr. --- src/intel/vulkan/anv_batch_chain.c | 4 1 file cha

[Mesa-dev] [RFC PATCH 12/14] anv/allocator: Rework chunk return to the state pool.

This commit tries to rework the code that split and returns chunks back to the state pool, while still keeping the same logic. The original code would get a chunk larger than we need and split it into pool->block_size. Then it would return all but the first one, and would split that first one into

[Mesa-dev] [RFC PATCH 09/14] anv: Validate the list of BOs from the block pool.

We now have multiple BOs in the block pool, but sometimes we still reference only the first one in some instructions, and use relative offsets in others. So we must be sure to add all the BOs from the block pool to the validation list when submitting commands. --- src/intel/vulkan/anv_batch_chain.

[Mesa-dev] [RFC PATCH 02/14] anv/allocator: Add anv_state_table.

Add a structure to hold anv_states. This table will initially be used to recicle anv_states, instead of relying on a linked list implemented in GPU memory. Later it could be used so that all anv_states just point to the content of this struct, instead of making copies of anv_states everywhere. TOD

[Mesa-dev] [RFC PATCH 14/14] anv/allocator: Add support for non-userptr.

If softpin is supported, create new BOs for the required size and add the respective BO maps. The other main change of this commit is that anv_block_pool_map() now returns the map for the BO that the given offset is part of. So there's no block_pool->map access anymore (when softpin is used. --- s

[Mesa-dev] [RFC PATCH 03/14] anv/allocator: Use anv_state_table on anv_state_pool_alloc.

Usage of anv_state_table_add is really annoying, see comment on the previous commit. --- src/intel/vulkan/anv_allocator.c | 96 +--- src/intel/vulkan/anv_private.h | 4 +- 2 files changed, 67 insertions(+), 33 deletions(-) diff --git a/src/intel/vulkan/anv_allocator

[Mesa-dev] [RFC PATCH 08/14] anv/allocator: Add support for a list of BOs in block pool.

So far we use only one BO (the last one created) in the block pool. When we switch to not use the userptr API, we will need multiple BOs. So add code now to store multiple BOs in the block pool. This has several implications, the main one being that we can't use pool->map as before. For that reaso

[Mesa-dev] [RFC PATCH 06/14] anv/allocator: Add getters for anv_block_pool.

We will need specially the anv_block_pool_map, to find the map relative to some BO that is not at the start of the block pool. --- src/intel/vulkan/anv_allocator.c | 23 --- src/intel/vulkan/anv_batch_chain.c | 5 +++-- src/intel/vulkan/anv_private.h | 7 +++ src/in

[Mesa-dev] [RFC PATCH 13/14] anv/allocator: Add padding information.

It's possible that we still have some space left in the block pool, but we try to allocate a state larger than that state. This means such state would start somewhere within the range of the old block_pool, and end after that range, within the range of the new size. That's fine when we use userptr

[Mesa-dev] [RFC PATCH 11/14] anv: Remove some asserts.

They won't be true anymore once we add support for multiple BOs with non-userptr. --- src/intel/vulkan/genX_gpu_memcpy.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c index 1bee1c6dc17..e20179fa675 100644 --- a/src/in

[Mesa-dev] [RFC PATCH 05/14] anv/allocator: Remove usage of anv_free_list.

Maybe we should already rename anv_free_list2 -> anv_free_list since the old one is gone. --- src/intel/vulkan/anv_allocator.c | 55 src/intel/vulkan/anv_private.h | 11 --- 2 files changed, 66 deletions(-) diff --git a/src/intel/vulkan/anv_allocator.c b/src

[Mesa-dev] [RFC PATCH 01/14] anv/tests: Fix block_pool_no_free test.

The test was checking whether -1 was smaller than an unsigned int, which is always false. So it was exiting early and never running until the end, since it would reach the condition (thread_max == -1). However, just fixing that is not enough. The test is currently getting the highest block on each

[Mesa-dev] [RFC PATCH 00/14] Do not use userptr in anv if softpin is available.

This series changes anv_block_pool to use a list of BO's instead of a single BO that gets reallocated and set with userptr. The main changes are: - The introduction of anv_state_table to track anv_states, and recycle them; - Addition of a list of BOs in anv_block_pool, instead of a single

[Mesa-dev] [PATCH] glapi: Fix DispatchSanity_test

--- src/mapi/glapi/gen/EXT_multisampled_render_to_texture.xml | 2 +- src/mapi/glapi/gen/es_EXT.xml | 2 ++ src/mapi/glapi/gen/gl_API.xml | 2 -- src/mesa/main/tests/dispatch_sanity.cpp | 3 +++ 4 files changed, 6 insertions

Re: [Mesa-dev] [PATCH 06/20] nir: rework force_unroll_array_access()

On Thu, Dec 6, 2018 at 9:09 PM Timothy Arceri wrote: > Here we rework force_unroll_array_access() so that we can reused > "reuse" > the induction variable detection in a following patch. > > Reviewed-by: Thomas Helland > --- > src/compiler/nir/nir_loop_analyze.c | 49

Re: [Mesa-dev] [PATCH 05/20] nir: factor out some of the complex loop unroll code to a helper

I haven't checked the details Acked-by: Jason Ekstrand On Thu, Dec 6, 2018 at 9:08 PM Timothy Arceri wrote: > Reviewed-by: Thomas Helland > --- > src/compiler/nir/nir_opt_loop_unroll.c | 115 ++--- > 1 file changed, 64 insertions(+), 51 deletions(-) > > diff --git a/src/c

Re: [Mesa-dev] [PATCH 04/20] nir: make use of new nir_cf_list_clone_and_reinsert() helper

3 and 4 are Reviewed-by: Jason Ekstrand On Thu, Dec 6, 2018 at 9:08 PM Timothy Arceri wrote: > Reviewed-by: Thomas Helland > --- > src/compiler/nir/nir_opt_loop_unroll.c | 76 ++ > 1 file changed, 28 insertions(+), 48 deletions(-) > > diff --git a/src/compiler/nir/nir

Re: [Mesa-dev] [PATCH 02/20] nir: clarify some nit_loop_info member names

Replacing min with max without changing any real code always looks a biit weird but it does make sense. :-) Reviewed-by: Jason Ekstrand On Thu, Dec 6, 2018 at 9:08 PM Timothy Arceri wrote: > Following commits will introduce additional fields such as > guessed_trip_count. Renaming these will he

Re: [Mesa-dev] [PATCH 2/3] intel/blorp: Make KSP a blorp_address instead of an offset.

I somewhat recant my statements below. Even in a driver that puts the full address in the offset field, having the BO pointer may still be useful for the purpose of adding it to a residency list somewhere. On Fri, Dec 7, 2018 at 4:13 PM Jason Ekstrand wrote: > I kind-of wonder if we want to all

Re: [Mesa-dev] [PATCH 3/3] intel/blorp: Add a simpler interface for softpin-only drivers.

I must say, I don't really like this patch. It seems like it's just trying to let you avoid writing two reloc functions which should, by and large, be no-ops for iris.That said, the way blorp does surface relocs is really annoying because it forces the reloc function to write in the value. Unf

Re: [Mesa-dev] [PATCH 2/3] intel/blorp: Make KSP a blorp_address instead of an offset.

I kind-of wonder if we want to allow for relocations and not surface state base address in which case you'd want to do something "real" with offset. Making this an address and then ignoring the buffer part entirely seems like it promises a bit too much. Then again, I don't think it's really hurtin

Re: [Mesa-dev] [PATCH 1/3] intel/blorp: Expand blorp_address::offset to be 64 bits.

Down with 32-bit offsets! Reviewed-by: Jason Ekstrand On Thu, Nov 29, 2018 at 2:24 AM Kenneth Graunke wrote: > In the softpin world, surface state base address may be a fixed 64-bit > address (with no associated BO). It makes sense to store this in the > offset field. But it needs to be the

Re: [Mesa-dev] [PATCH 01/20] nir: small tidy ups for nir_loop_analyze()

Reviewed-by: Jason Ekstrand On Thu, Dec 6, 2018 at 9:08 PM Timothy Arceri wrote: > Reviewed-by: Thomas Helland > --- > src/compiler/nir/nir_loop_analyze.c | 31 ++--- > 1 file changed, 10 insertions(+), 21 deletions(-) > > diff --git a/src/compiler/nir/nir_loop_analyze

[Mesa-dev] [PATCH 1/2] pci_ids: add new vega10 pci ids

Signed-off-by: Alex Deucher Cc: mesa-sta...@lists.freedesktop.org --- include/pci_ids/radeonsi_pci_ids.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 35ea3559b02..f7defc4197a 100644 --- a/

[Mesa-dev] [PATCH 2/2] pci_ids: add new vega20 pci id

Signed-off-by: Alex Deucher Cc: mesa-sta...@lists.freedesktop.org --- include/pci_ids/radeonsi_pci_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index f7defc4197a..a2bc9213207 100644 --- a/include/pci_ids/radeons

Re: [Mesa-dev] [PATCH 54/59] intel/compiler: add a brw_reg_type_is_integer helper

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > --- > src/intel/compiler/brw_reg_type.h | 18 ++ > 1 file changed, 18 insertions(+) > > diff --git a/src/intel/compiler/brw_reg_type.h > b/src/intel/compiler/brw_reg_type.h > index ffbec90d3f

Re: [Mesa-dev] [PATCH 53/59] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > There are no 8-bit immediates, so assert in that case. > 16-bit immediates are replicated in each word of a 32-bit immediate, so > we only need to check the lower 16-bits. > --- > src/intel/compiler/brw_shader.cpp | 20 ++

Re: [Mesa-dev] [PATCH v2] docs: Document GitLab merge request process (email alternative)

Hi, On Sat, 8 Dec 2018 at 05:15, Eric Engestrom wrote: > On Friday, 2018-12-07 10:19:23 +0100, Erik Faye-Lund wrote: > > Automated emails (and perhaps IRC bot) would be really nice. > > Agreed. Email would be great to help with the transition. > There's work currently being done on GitLab to allo

Re: [Mesa-dev] [PATCH 52/59] anv/device: expose shaderInt8 feature

51 and 52 should probably be rolled together. For that matter, I don't think we need 6 patches just to add two SPIR-V capabilities and advertise one extension. Maybe roll the two SPIR-V patches together, add one or two for the extension and the enables? On Tue, Dec 4, 2018 at 1:18 AM Iago Toral

Re: [Mesa-dev] [PATCH 49/59] intel/eu: force stride of 2 on NULL register for Byte instructions

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > The hardware only allows a stride of 1 on a Byte destination for raw > byte MOV instructions. This is required even when the destination > is the NULL register. > > Rather than making sure that we emit a prop

Re: [Mesa-dev] [PATCH 48/59] intel/compiler: implement isign for int8

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > --- > src/intel/compiler/brw_fs_nir.cpp | 25 + > 1 file changed, 21 insertions(+), 4 deletions(-) > > diff --git a/src/intel/compiler/brw_fs_nir.cpp > b/src/intel/compiler/brw_fs_nir

Re: [Mesa-dev] [PATCH 46/59] intel/compiler: fix integer to/from half-float in atom platforms

We are starting to get a *lot* of special cases in the conversion code. I'm not sure what the best thing to do is. Maybe some master conversion function that just does it all? Maybe some NIR lowering? In any case, I think we can do better than the pile of special cases we are starting to accumul

Re: [Mesa-dev] [PATCH 42/59] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > Particularly, we need the same lowewrings we use for 16-bit > integers. > --- > src/intel/compiler/brw_nir.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/intel/compiler/brw_ni

Re: [Mesa-dev] [PATCH 40/59] anv/extensions: expose VK_KHR_shader_float16_int8 on gen8+

rb On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > --- > src/intel/vulkan/anv_extensions.py | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/intel/vulkan/anv_extensions.py > b/src/intel/vulkan/anv_extensions.py > index 7c81228f705..9ca42d998ef 100644 > --- a/src/intel/vul

Re: [Mesa-dev] [PATCH 39/59] anv/device: expose support for shaderFloat16 in gen8+

Pending review on previous patches. 37 and 39 are Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > --- > src/intel/vulkan/anv_device.c | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_

Re: [Mesa-dev] [PATCH 36/59] compiler/spirv: add implementation to check for SpvCapabilityFloat16 support

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > --- > src/compiler/shader_info.h| 1 + > src/compiler/spirv/spirv_to_nir.c | 4 +++- > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/src/compiler/shader_info.h b/src/compiler/shade

Re: [Mesa-dev] [PATCH 34/59] intel/compiler: fix ddy for half-float in gen8

On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > We use ALign16 mode for this, since it is more convenient, but the PRM > for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region > restrictions', Section '1. Special Restrictions': > >"In Align16 mode, the channel sele

Re: [Mesa-dev] [PATCH 33/59] intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > The implementation of these opcodes in the generator assumes that their > arguments are packed, and it generates register regions based on that > assumption. While this expectation is reasonable for 32-bit, Expectation, sure, but if som

Re: [Mesa-dev] [PATCH 32/59] intel/compiler: fix 16-bit float ddx and ddy for SIMD8

And here we are I think I'd still like byte_offset better but, either way patches 31 and 32 are Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > In SIMD8 we pack 2 vector components in a single SIMD register, so > for example, component Y of a 16-bit v

Re: [Mesa-dev] [PATCH 31/59] intel/compiler: fix ddx and ddy for 16-bit float

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > We were assuming 32-bit elements. > --- > src/intel/compiler/brw_fs_generator.cpp | 34 + > 1 file changed, 18 insertions(+), 16 deletions(-) > > diff --git a/src/intel/compiler/brw_fs_generator.cpp > b/src/intel/

Re: [Mesa-dev] [PATCH 29/59] intel/compiler: don't propagate HF immediates to 3-src instructions

Seems reasonable though I thought you had patches to the constant combining to fix this. Maybe they'll be ready in time that we won't need this? On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > 3-src instructions don't support immediates, but since 36bc5f06dd22, > we allow them on MAD

Re: [Mesa-dev] [PATCH v2] docs: Document GitLab merge request process (email alternative)

On Friday, 2018-12-07 10:19:23 +0100, Erik Faye-Lund wrote: > On Wed, 2018-12-05 at 21:46 -0600, Jason Ekstrand wrote: > > On Wed, Dec 5, 2018 at 7:05 PM Jordan Justen < > > jordan.l.jus...@intel.com> wrote: > > > On 2018-12-05 15:44:18, Jason Ekstrand wrote: > > > > On Wed, Dec 5, 2018 at 5:32 PM

Re: [Mesa-dev] [PATCH 28/59] intel/compiler: set correct precision fields for 3-source float instructions

On Wed, Dec 5, 2018 at 7:14 AM Pohjolainen, Topi wrote: > On Wed, Dec 05, 2018 at 02:04:16PM +0100, Iago Toral wrote: > > On Wed, 2018-12-05 at 14:58 +0200, Pohjolainen, Topi wrote: > > > On Tue, Dec 04, 2018 at 08:16:52AM +0100, Iago Toral Quiroga wrote: > > > > Source0 and Destination extract t

Re: [Mesa-dev] [PATCH 00/11] i965 shader debug through KHR_debug

Ilia Mirkin writes: > On Thu, Dec 6, 2018 at 7:36 PM Mark Janes wrote: >> >> This series provides Intel shader compilation debug information via >> KHR_debug. Previously, shader assembly and related compilation >> artifacts were dumped to stderr. Tools associating compilation >> artifacts with

Re: [Mesa-dev] [PATCH] meson: Add nir_algebraic_parser_test to suites

On Friday, 2018-12-07 09:16:38 -0800, Dylan Baker wrote: > Just to make it easier to run a nir tests together. > > Fixes: a0ae12ca91a45f81897e774019cde9bd081f03a0 >("nir/algebraic: Add unit tests for bitsize validation") Reviewed-by: Eric Engestrom > --- > src/compiler/nir/meson.build

Re: [Mesa-dev] [PATCH 23/59] intel/compiler: Extended Math is limited to SIMD8 on half-float

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > From the Skylake PRM, Extended Math Function: > > "The execution size must be no more than 8 when half-floats >are used in source or destination operand." > > Earlier generations do not support Extended Math with half-float. > --- >

Re: [Mesa-dev] [PATCH 22/59] compiler/nir: add lowering for 16-bit ldexp

On Wed, Dec 5, 2018 at 5:32 AM Pohjolainen, Topi wrote: > On Wed, Dec 05, 2018 at 12:26:06PM +0100, Iago Toral wrote: > > On Wed, 2018-12-05 at 13:20 +0200, Pohjolainen, Topi wrote: > > > On Wed, Dec 05, 2018 at 11:53:44AM +0100, Iago Toral wrote: > > > > On Wed, 2018-12-05 at 11:39 +0200, Pohjol

Re: [Mesa-dev] [PATCH 16/59] intel/compiler: implement 16-bit fsign

I think it's probably less code to just make a separate 16-bit case. On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > --- > src/intel/compiler/brw_fs_nir.cpp | 27 +-- > 1 file changed, 21 insertions(+), 6 deletions(-) > > diff --git a/src/intel/compiler/brw_fs

[Mesa-dev] [PATCH 29/38] ac/nir: implement 16-bit pack/unpack opcodes

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 24 1 file changed, 24 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index aac3330c0d..d69135cc25 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/com

[Mesa-dev] [PATCH 24/38] ac/nir: make ac_find_lsb work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 31 +-- 1 file changed, 5 insertions(+), 26 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 6266058b77..754ceda89b 100644 --- a/src/amd/common/ac_llvm_build.

[Mesa-dev] [PATCH 38/38] radv: expose float16, int16 and int8 features and extensions

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_device.c | 17 + src/amd/vulkan/radv_extensions.py | 4 src/amd/vulkan/radv_shader.c | 3 +++ 3 files changed, 24 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index ad057a

[Mesa-dev] [PATCH 31/38] ac/nir, radv: create an array of varying output types

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 68 +++ src/amd/common/ac_shader_abi.h| 1 + src/amd/vulkan/radv_nir_to_llvm.c | 3 ++ 3 files changed, 72 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llv

[Mesa-dev] [PATCH 37/38] ac/nir: have nir_op_f2f16 round to zero

In the hope that one day LLVM will then be able to generate code with vectorized v_cvt_pkrtz_f16_f32 instructions. Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac

[Mesa-dev] [PATCH 30/38] ac/nir: add 8-bit and 16-bit types to glsl_base_to_llvm_type

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 8 1 file changed, 8 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index d69135cc25..e4ae85a1ae 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm

[Mesa-dev] [PATCH 20/38] compiler/nir: add lowering option for 16-bit ffma

The lowering needs to be disabled for sufficient precision to pass deqp-vk's 16-bit fma test on radv. Signed-off-by: Rhys Perry --- src/broadcom/compiler/nir_to_vir.c| 1 + src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 4 +++- src/gallium/drivers/radeon

[Mesa-dev] [PATCH 35/38] ac,radv: run LLVM's SLP vectorizer

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_util.c | 9 ++--- src/amd/common/ac_llvm_util.h | 1 + src/amd/vulkan/radv_shader.c | 3 +++ 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c index dc9b684e9d..32

[Mesa-dev] [PATCH 23/38] nir: make bitfield_reverse and ifind_msb work with all integers

Signed-off-by: Rhys Perry --- src/compiler/nir/nir_opcodes.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index 4ef4ecc6f2..962971c650 100644 --- a/src/compiler/nir/nir_opcodes.py +++ b/src/compiler/nir/

[Mesa-dev] [PATCH 34/38] radv: handle all fragment output types

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 55 --- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 3d367c1378..342b79274a 100644 --- a/src/amd/vulkan/rad

[Mesa-dev] [PATCH 28/38] ac/nir: make ac_build_bitfield_reverse work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 3990a1f56d..68ea6078d3 100644 --- a/src/amd/common/ac_llvm_build.c +++

[Mesa-dev] [PATCH 26/38] ac/nir: implement 8 and 16 bit ac_build_imsb

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 4 1 file changed, 4 insertions(+) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 0123f3e31d..2172d81f8b 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd/common/ac_llvm_build.c @@ -16

[Mesa-dev] [PATCH 25/38] ac/nir: make ac_build_umsb work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 38 +++--- 1 file changed, 7 insertions(+), 31 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 754ceda89b..0123f3e31d 100644 --- a/src/amd/common/ac_llvm_bui

[Mesa-dev] [PATCH 22/38] ac/nir: implement 8 and 16 bit ac_build_readlane

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index f394d16bc9..6266058b77 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd/comm

[Mesa-dev] [PATCH 27/38] ac/nir: make ac_build_bit_count work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +++-- 1 file changed, 7 insertions(+), 26 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 2172d81f8b..3990a1f56d 100644 --- a/src/amd/common/ac_llvm_buil

[Mesa-dev] [PATCH 32/38] ac/nir: store all outputs as f32

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 13 - src/amd/vulkan/radv_nir_to_llvm.c | 22 +- 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index fa7b8c70f0..b

[Mesa-dev] [PATCH 21/38] ac/nir: implement 16-bit ac_build_ddxy

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 17 ++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index e85c178f78..f394d16bc9 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/am

[Mesa-dev] [PATCH 36/38] ac/nir: generate better code for nir_op_f2f16_rtz

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index b4418af50a..92b773981b 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_

[Mesa-dev] [PATCH 33/38] radv: store all fragment shader inputs as f32

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index e5e4637f0d..3d367c1378 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c ++

[Mesa-dev] [PATCH 19/38] ac/nir: implement 16-bit shifts

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 517da7ba9b..aac3330c0d 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/comm

[Mesa-dev] [PATCH 08/38] ac/nir: make ac_build_clamp work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index cc7c6da5a4..1ef28323d1 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd/com

[Mesa-dev] [PATCH 15/38] ac/nir: implement half-float nir_op_ldexp

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index b447da092f..bb7c421606 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_

[Mesa-dev] [PATCH 10/38] ac/nir: make ac_build_isign work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 27 --- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 0a1987c65b..fa5c68d1b6 100644 --- a/src/amd/common/ac_llvm_build.c ++

[Mesa-dev] [PATCH 11/38] ac/nir: make ac_build_fsign work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index fa5c68d1b6..c85f9a214e 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd

[Mesa-dev] [PATCH 01/38] ac: add various helpers for float16/int16/int8

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 123 ++-- src/amd/common/ac_llvm_build.h | 22 +- src/amd/common/ac_nir_to_llvm.c | 30 3 files changed, 154 insertions(+), 21 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/sr

[Mesa-dev] [PATCH 13/38] ac/nir: implement half-float nir_op_frcp

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index ef850d6d22..7084b390d2 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_n

[Mesa-dev] [PATCH 16/38] radv: lower 16-bit flrp

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_shader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 456c462a23..9ba20ac72e 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -53,6 +53,7 @@ s

[Mesa-dev] [PATCH 04/38] ac/nir: fix 16-bit ssbo stores

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 31fb77290c..535a47d790 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@

[Mesa-dev] [PATCH 14/38] ac/nir: implement half-float nir_op_frsq

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 7084b390d2..b447da092f 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_n

[Mesa-dev] [PATCH 18/38] ac/nir: make emit_b2i work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 459d9c119c..517da7ba9b 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/a

[Mesa-dev] [PATCH 17/38] ac/nir: support half floats in emit_b2f

This seems to generate fine code, even though the IR is a bit ugly. Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index bb7c421606

[Mesa-dev] [PATCH 12/38] ac/nir: make ac_build_fdiv support 16-bit floats

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index c85f9a214e..e85c178f78 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd/common/ac_llvm_bu

[Mesa-dev] [PATCH 05/38] ac/nir: implement 8-bit nir_load_const_instr

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 1 file changed, 4 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 535a47d790..6d0d2cbd55 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @

[Mesa-dev] [PATCH 07/38] ac/nir: fix 64-bit nir_op_f2f16_rtz

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 7c827b443b..ef850d6d22 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@

[Mesa-dev] [PATCH 09/38] ac/nir: make ac_build_fract work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 13 +++-- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 1ef28323d1..0a1987c65b 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd/co

[Mesa-dev] [PATCH 02/38] ac/nir: implement 8-bit push constant, ssbo and ubo loads

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 37 +++-- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 2e9fd7b689..8910dabb3d 100644 --- a/src/amd/common/ac_nir_to

[Mesa-dev] [PATCH 06/38] ac/nir: implement 8-bit conversions

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 6d0d2cbd55..7c827b443b 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/comm

[Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

This series add support for: - VK_KHR_shader_float16_int8 - VK_AMD_gpu_shader_half_float - VK_AMD_gpu_shader_int16 - VK_KHR_8bit_storage on VI+. Half floats are currently disabled on LLVM 7 because of a bug causing large memory usage and long (or unbounded) compilation times with some tests. It de

[Mesa-dev] [PATCH 03/38] ac/nir: implement 8-bit ssbo stores

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 8910dabb3d..31fb77290c 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

Re: [Mesa-dev] [PATCH 15/59] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9

I haven't checked the HW docs but Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > Extended math desn't support half-float on these generations. > --- > src/intel/compiler/brw_nir.c | 13 - > 1 file changed, 12 insertions(+), 1 deletion(-) > >

[Mesa-dev] [PATCH] meson: Add nir_algebraic_parser_test to suites

Just to make it easier to run a nir tests together. Fixes: a0ae12ca91a45f81897e774019cde9bd081f03a0 ("nir/algebraic: Add unit tests for bitsize validation") --- src/compiler/nir/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/

Re: [Mesa-dev] [PATCH 14/59] intel/compiler: lower some 16-bit float operations to 32-bit

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > The hardware doesn't support half-float for these. > --- > src/intel/compiler/brw_nir.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir

Re: [Mesa-dev] Mesa (master): mesa: Add core support for EXT_multisampled_render_to_texture{, 2}

On Fri, Dec 7, 2018 at 1:49 AM Michel Dänzer wrote: > > On 2018-12-07 2:02 a.m., GitLab Mirror wrote: > > Module: Mesa > > Branch: master > > Commit: 1b331ae505e63033634d9f5267ca1949336f75d8 > > URL: > > http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b331ae505e63033634d9f5267ca1949336f75d8

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