On 10/23/2018 08:17 AM, Tapani Pälli wrote:
>
> On 10/23/18 8:56 AM, Eduardo Lima Mitev wrote:
>> There exists _mesa_components_in_format() which already includes
>> all cases handled in _mesa_base_format_component_count().
>
> I guess the idea here was that one function only covers 'base formats
On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand wrote:
>
> D3D booleans use a 32-bit 0/-1 representation. Because this previously
> matched NIR exactly, we didn't have to really optimize for it. Now that
> we have 1-bit booleans, we need some specific optimizations to chew
> through the D3D12-st
On 10/23/18 8:56 AM, Eduardo Lima Mitev wrote:
There exists _mesa_components_in_format() which already includes
all cases handled in _mesa_base_format_component_count().
I guess the idea here was that one function only covers 'base formats'
and other one all formats. But I guess none of the u
There exists _mesa_components_in_format() which already includes
all cases handled in _mesa_base_format_component_count().
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/main/glformats.c | 27 ---
src/mesa/main/glformats.h | 3 ---
src/
Am Di., 23. Okt. 2018 um 01:43 Uhr schrieb Jason Ekstrand
:
>
> On Mon, Oct 22, 2018 at 6:20 PM Alyssa Rosenzweig
> wrote:
>>
>> For what it's worth, Midgard has real integers (including int32
>> support), using hardware-level D3D10 boolean conventions. I'm trying to
>> wrap my head around how th
On 10/22/18 11:47 PM, Matt Turner wrote:
On Mon, Sep 24, 2018 at 4:20 AM Tapani Pälli wrote:
From: Scott D Phillips
Rename the (un)map_gtt functions to (un)map_map (map by
returning a map) and add new functions (un)map_tiled_memcpy that
return a shadow buffer populated with the intel_tiled
On Thu, 2018-10-18 at 14:31 -0400, Ilia Mirkin wrote:
> On Thu, Oct 18, 2018 at 2:26 PM Erik Faye-Lund
> wrote:
> > On Oct 18, 2018 18:21, Ilia Mirkin wrote:
> >
> > Have you verified that this works OK on GLES2? This extension
> > enables
> > online compression, which isn't normally available i
I think so?
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On October 22, 2018 20:13:25 Alyssa Rosenzweig wrote:
If you want to set me straight, that's probably the better patch to
argue it out. :)
No, I thought about it; you're right. I understand my hardware (and NIR)
much better now than what I wrote the earlier patch; you have now shown
me the er
> If you want to set me straight, that's probably the better patch to
> argue it out. :)
No, I thought about it; you're right. I understand my hardware (and NIR)
much better now than what I wrote the earlier patch; you have now shown
me the error of my ways :)
Nothing special should be needed for
Eric Engestrom writes:
> Fixes errors thrown by GCC's Undefined Behaviour sanitizer (ubsan) every
> time this macro is used.
Reviewed-by: Eric Anholt
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h
Eric Anholt writes:
> This will be used on V3D to cut down the size of the VS inputs in the VPM
> (memory area for sharing data between shader stages).
Ping on this one. I'd love to land the series behind it.
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On Monday, October 22, 2018 5:39:39 PM PDT Lionel Landwerlin wrote:
> Pointer arithmetic...
>
> v2: s/4/sizeof(uint32_t)/ (Eric)
>
> v3: Give bytes to print_batch() in error_decode (Lionel)
> Make clear what values we're dealing with in error_decode (Lionel)
>
> Signed-off-by: Lionel Landwer
Pointer arithmetic...
v2: s/4/sizeof(uint32_t)/ (Eric)
v3: Give bytes to print_batch() in error_decode (Lionel)
Make clear what values we're dealing with in error_decode (Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Eric Engestrom (v2)
---
src/intel/common/gen_batch_decoder.c
On 10/22/2018 05:09 PM, Alyssa Rosenzweig wrote:
>> Right. Sorry. I forgot who's working on what chip these days. Maybe Ilia
>> can CC the right person.
>
> No worries at all! It may well have been me (I had touched the b2f code;
> our hardware lacks a dedicated instruction and needs `iand 1.0`
On 10/22/2018 04:31 PM, Jason Ekstrand wrote:
> The conon_bit_class and canon_var_class variables got switched.
canon :)
Reviewed-by: Ian Romanick
>
> Fixes: 932c650e0b "nir/algebraic: Loosen a restriction on variables"
> Reported-by: Ian Romanick
> ---
> src/compiler/nir/nir_algebrai
> Right. Sorry. I forgot who's working on what chip these days. Maybe Ilia
> can CC the right person.
No worries at all! It may well have been me (I had touched the b2f code;
our hardware lacks a dedicated instruction and needs `iand 1.0` to do
the conversion). I'm not sure which hardware lacks
Jason Ekstrand writes:
> We have a helper that does exactly what the bany_inequal was doing. It
> emits the same code but is a bit higher level and is designed to operate
> on a bvec4.
Patch 6, 8-10 also r-b. I couldn't make sense of patch 7's optimization
pass beforehand, so I failed to revie
On Mon, Oct 22, 2018 at 6:26 PM Ian Romanick wrote:
> On 10/22/2018 03:13 PM, Jason Ekstrand wrote:
> > These all assume the 0/~0 representation of booleans. We'll turn them
> > back on before too long.
> > ---
> > src/compiler/nir/nir_opt_algebraic.py | 5 -
> > 1 file changed, 5 deletions
On Mon, Oct 22, 2018 at 6:22 PM Ian Romanick wrote:
> On 10/22/2018 03:13 PM, Jason Ekstrand wrote:
> > This commit adds support for 1-bit booleans and integers. Booleans
>
> I've noticed this in some of the patches... Boolean is a proper name, so
> it should be capitalized everywhere.
>
I did
On Mon, Oct 22, 2018 at 6:13 PM Ilia Mirkin wrote:
> On Mon, Oct 22, 2018 at 6:16 PM Jason Ekstrand
> wrote:
> >
> > This should be useful for drivers that don't support real integers.
> >
> > Cc: Alyssa Rosenzweig
> > ---
> > src/compiler/Makefile.sources | 1 +
> > src/compile
On Mon, Oct 22, 2018 at 6:20 PM Alyssa Rosenzweig
wrote:
> For what it's worth, Midgard has real integers (including int32
> support), using hardware-level D3D10 boolean conventions. I'm trying to
> wrap my head around how this interacts with 5d85a0a.
>
Right. Sorry. I forgot who's working on
The conon_bit_class and canon_var_class variables got switched.
Fixes: 932c650e0b "nir/algebraic: Loosen a restriction on variables"
Reported-by: Ian Romanick
---
src/compiler/nir/nir_algebraic.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_algebr
On Mon, Oct 22, 2018 at 6:28 PM Ian Romanick wrote:
> On 10/20/2018 11:01 AM, Jason Ekstrand wrote:
> > Previously, we would fail if a variable had an assigned but unknown bit
> > size X and we tried to assign it an actual bit size. However, this is
> > ok because, at the time we do the search,
On Mon, Oct 22, 2018 at 6:06 PM Ian Romanick wrote:
> On 10/22/2018 03:13 PM, Jason Ekstrand wrote:
> > ---
> > src/compiler/nir/nir_lower_alu_to_scalar.c | 8 ++--
> > src/compiler/nir/nir_opcodes.py| 46 +++---
> > src/compiler/nir/nir_opcodes_c.py | 8 ++
On 10/20/2018 11:01 AM, Jason Ekstrand wrote:
> Previously, we would fail if a variable had an assigned but unknown bit
> size X and we tried to assign it an actual bit size. However, this is
> ok because, at the time we do the search, the variable does have an
> actual bit size and it will match
On 10/22/2018 03:13 PM, Jason Ekstrand wrote:
> These all assume the 0/~0 representation of booleans. We'll turn them
> back on before too long.
> ---
> src/compiler/nir/nir_opt_algebraic.py | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/src/compiler/nir/nir_opt_algebraic.py
> b/s
On Mon, Oct 22, 2018 at 6:16 PM Eric Anholt wrote:
> Jason Ekstrand writes:
>
> > diff --git a/src/mesa/drivers/dri/i965/brw_program.c
> b/src/mesa/drivers/dri/i965/brw_program.c
> > index f5ebd3c3b05..78050cda359 100644
> > --- a/src/mesa/drivers/dri/i965/brw_program.c
> > +++ b/src/mesa/driver
On 10/22/2018 03:13 PM, Jason Ekstrand wrote:
> This commit adds support for 1-bit booleans and integers. Booleans
I've noticed this in some of the patches... Boolean is a proper name, so
it should be capitalized everywhere.
> obviously take a value of true or false. Because we have to define t
For what it's worth, Midgard has real integers (including int32
support), using hardware-level D3D10 boolean conventions. I'm trying to
wrap my head around how this interacts with 5d85a0a.
I'm tempted to think the standard lower_bool_to_int32 pass would work,
with an emulated b2f instruction in th
Jason Ekstrand writes:
> diff --git a/src/mesa/drivers/dri/i965/brw_program.c
> b/src/mesa/drivers/dri/i965/brw_program.c
> index f5ebd3c3b05..78050cda359 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.c
> +++ b/src/mesa/drivers/dri/i965/brw_program.c
> @@ -91,14 +91,14 @@ brw_create_nir(s
On Mon, Oct 22, 2018 at 6:16 PM Jason Ekstrand wrote:
>
> This should be useful for drivers that don't support real integers.
>
> Cc: Alyssa Rosenzweig
> ---
> src/compiler/Makefile.sources | 1 +
> src/compiler/nir/meson.build | 1 +
> src/compiler/nir/nir_lower_b
On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand wrote:
>
> D3D booleans use a 32-bit 0/-1 representation. Because this previously
> matched NIR exactly, we didn't have to really optimize for it. Now that
> we have 1-bit booleans, we need some specific optimizations to chew
> through the D3D12-st
https://bugs.freedesktop.org/show_bug.cgi?id=108508
--- Comment #6 from Ahmed Elsayed ---
Created attachment 142145
--> https://bugs.freedesktop.org/attachment.cgi?id=142145&action=edit
Mafia III
It gets better and better :D
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Patches 1 through 13 are
Reviewed-by: Ian Romanick
The rest are going to take a bit more time and deep thought.
On 10/22/2018 03:13 PM, Jason Ekstrand wrote:
> This is something that Connor and I have talked about quite a bit over the
> last couple of months. The core idea is to replace NIR's
On 10/22/2018 03:13 PM, Jason Ekstrand wrote:
> ---
> src/compiler/nir/nir_lower_alu_to_scalar.c | 8 ++--
> src/compiler/nir/nir_opcodes.py| 46 +++---
> src/compiler/nir/nir_opcodes_c.py | 8 ++--
> 3 files changed, 31 insertions(+), 31 deletions(-)
>
> di
On Mon, Oct 22, 2018 at 5:50 PM Ian Romanick wrote:
> I think a better description is "nir/search: Use nir_imm_* helpers".
> Using nir_builder is just a prerequisite to doing that.
>
Good call. The new commit message is:
nir/search: Use the nir_imm_* helpers from nir_builder
This requ
I think a better description is "nir/search: Use nir_imm_* helpers".
Using nir_builder is just a prerequisite to doing that.
On 10/22/2018 03:13 PM, Jason Ekstrand wrote:
> ---
> src/compiler/nir/nir_algebraic.py | 14 ++--
> src/compiler/nir/nir_search.c | 111 --
On Mon, Oct 22, 2018 at 2:14 PM Sagar Ghuge wrote:
>
>
>
> On 10/22/18 10:34 AM, Matt Turner wrote:
> > On Fri, Oct 5, 2018 at 11:15 AM Sagar Ghuge wrote:
> >>
> >> avoid misinterpretation of encoded immediate values in instruction and
> >> disassembled output.
> >>
> >> Signed-off-by: Sagar Ghug
This should be useful for drivers that don't support real integers.
Cc: Alyssa Rosenzweig
---
src/compiler/Makefile.sources | 1 +
src/compiler/nir/meson.build | 1 +
src/compiler/nir/nir_lower_bool_to_float.c | 181 +
3 files changed, 183 inser
---
src/compiler/nir/nir_opt_algebraic.py | 4
1 file changed, 4 insertions(+)
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index 6c767501a51..f0861c4411d 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebrai
D3D booleans use a 32-bit 0/-1 representation. Because this previously
matched NIR exactly, we didn't have to really optimize for it. Now that
we have 1-bit booleans, we need some specific optimizations to chew
through the D3D12-style booleans.
---
src/compiler/nir/nir_opt_algebraic.py | 13
---
src/compiler/nir/nir_algebraic.py | 43 +++
src/compiler/nir/nir_opt_algebraic.py | 1 -
2 files changed, 4 insertions(+), 40 deletions(-)
diff --git a/src/compiler/nir/nir_algebraic.py
b/src/compiler/nir/nir_algebraic.py
index 9d187ca36d7..b880aa0dc66 100644
---
---
src/compiler/nir/nir.h | 24 -
src/compiler/nir/nir_loop_analyze.c| 28 +-
src/compiler/nir/nir_opt_if.c | 2 +-
src/compiler/nir/nir_opt_peephole_select.c | 2 +-
src/compiler/nir/nir_opt_undef.c | 2 +-
src/compiler/spirv/
---
src/compiler/nir/nir_builder_opcodes_h.py | 44 +--
1 file changed, 1 insertion(+), 43 deletions(-)
diff --git a/src/compiler/nir/nir_builder_opcodes_h.py
b/src/compiler/nir/nir_builder_opcodes_h.py
index a9de0e4ea47..e600093e9f6 100644
--- a/src/compiler/nir/nir_builder_
---
src/compiler/nir/nir_builder.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index eaba5cfe448..2f2fc49c448 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -212,9 +212,
This commit contains three related changes. First, we define boolN_t
for N = 8, 16, and 64 and move the definition of boolN_vec to the loop
with the other vec definitions. Second, there's no reason why we need
the != 0 on the source because that happens implicitly when it's
converted to bool. Th
These all assume the 0/~0 representation of booleans. We'll turn them
back on before too long.
---
src/compiler/nir/nir_opt_algebraic.py | 5 -
1 file changed, 5 deletions(-)
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index 8b24daddfdc..5a4e78
Generated with a little hand-editing and the following sed commands:
sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
sed -i 's/nir_op_bany_inequal/n
This commit adds support for 1-bit booleans and integers. Booleans
obviously take a value of true or false. Because we have to define the
semantics of 1-bit signed and unsigned integers, we define uint1_t to
take values of 0 and 1 and int1_t to take values of 0 and -1. 1-bit
arithmetic is then w
---
src/compiler/nir/nir_algebraic.py | 35 +++
1 file changed, 35 insertions(+)
diff --git a/src/compiler/nir/nir_algebraic.py
b/src/compiler/nir/nir_algebraic.py
index d2374d3216a..9d187ca36d7 100644
--- a/src/compiler/nir/nir_algebraic.py
+++ b/src/compiler/nir/nir
---
src/compiler/glsl/glsl_to_nir.cpp | 4 ++--
src/compiler/nir/nir.h| 2 +-
src/compiler/nir/nir_opcodes_c.py | 8
src/compiler/nir_types.h | 4 +++-
src/compiler/spirv/spirv_to_nir.c | 2 +-
5 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/src/compil
---
src/compiler/nir/nir_builder_opcodes_h.py | 44 ++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_builder_opcodes_h.py
b/src/compiler/nir/nir_builder_opcodes_h.py
index e600093e9f6..a9de0e4ea47 100644
--- a/src/compiler/nir/nir_builder_
We also enable it in all of the NIR drivers.
Cc: Timothy Arceri
Cc: Eric Anholt
Cc: Rob Clark
Cc: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_shader.c | 2 +
src/broadcom/compiler/vir.c | 2 +
src/compiler/Makefile.sources | 1 +
src/com
---
src/compiler/nir/nir_lower_alu_to_scalar.c | 8 ++--
src/compiler/nir/nir_opcodes.py| 46 +++---
src/compiler/nir/nir_opcodes_c.py | 8 ++--
3 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c
b/src
Generated with a little hand-editing and the following sed commands:
sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
sed -i 's/nir_op_bany_inequal/n
---
src/compiler/nir/nir_lower_alu_to_scalar.c | 4 +++
src/compiler/nir/nir_opcodes.py| 29 ++
2 files changed, 33 insertions(+)
diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c
b/src/compiler/nir/nir_lower_alu_to_scalar.c
index e424dff25c4..4f97472a87d 1
---
src/intel/compiler/brw_nir.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 1cd56861578..cf5a4a96d67 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -674,7 +674,7 @@ brw
Instead of initializing them manually, just use the type that we already
have sitting there.
---
src/compiler/spirv/vtn_subgroup.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_subgroup.c
b/src/compiler/spirv/vtn_subgroup.c
index ecec3aa62
Previously, we would always pull the bit size from the destination which
is wrong for opcodes like nir_ilt where the sources are variable-sized
but the destination is a fixed size. We were getting lucky before
because nir_op_ilt returns a 32-bit value and basically everyone who
uses spec constants
We have a helper that does exactly what the bany_inequal was doing. It
emits the same code but is a bit higher level and is designed to operate
on a bvec4.
---
src/mesa/program/prog_to_nir.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/program/prog_to_nir.c b/src/m
This isn't a great solution for bit-sizes but we don't have a
particularly convenient way to get a bit size from the system value enum
and this keeps the lowering pass from changing it.
---
src/compiler/nir/nir_lower_system_values.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/
---
src/compiler/nir/nir_algebraic.py | 14 ++--
src/compiler/nir/nir_search.c | 111 --
src/compiler/nir/nir_search.h | 9 ++-
3 files changed, 43 insertions(+), 91 deletions(-)
diff --git a/src/compiler/nir/nir_algebraic.py
b/src/compiler/nir/nir_algebrai
They do the same thing in the end but i2b is a bit simpler. Also, let's
clean up the mess of code for SSBO handling with one line of builder.
---
src/compiler/glsl/glsl_to_nir.cpp | 24 +---
1 file changed, 5 insertions(+), 19 deletions(-)
diff --git a/src/compiler/glsl/glsl_
---
src/compiler/nir/nir_builder.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index 5ea0a5a2637..3271a480520 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -25,6 +25,7 @@
---
src/amd/vulkan/radv_shader.c | 4 +--
src/compiler/nir/nir.h| 12 +++
src/compiler/nir/nir_validate.c | 14 ++---
src/compiler/nir/tests/vars_tests.cpp | 38 +++
src/intel/compiler/brw_nir.c | 8 ++---
sr
Instead of doing our own constant folding, we just emit instructions and
let constant folding happen. This is substantially simpler and lets us
use the nir_imm_bool helper instead of dealing with the const_value's
ourselves.
---
src/compiler/nir/nir_opt_if.c | 91 -
---
src/compiler/nir/nir_opt_constant_folding.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/compiler/nir/nir_opt_constant_folding.c
b/src/compiler/nir/nir_opt_constant_folding.c
index e2920e6b3fd..05b47d4c0fe 100644
--- a/src/compiler/nir/nir_opt_constant_folding.c
+++ b/src/compile
---
src/compiler/nir/nir_builder.h| 25 ++-
src/compiler/nir/nir_lower_int64.c| 2 +-
src/compiler/nir/nir_lower_returns.c | 4 +--
src/compiler/nir/nir_lower_subgroups.c| 2 +-
src/compiler/nir/nir_opt_intrinsics.c | 2 +-
s
Missed one while converting to the nir_src_as_* helpers.
---
src/compiler/nir/nir_opt_constant_folding.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/compiler/nir/nir_opt_constant_folding.c
b/src/compiler/nir/nir_opt_constant_folding.c
index 05b47d4c0fe..5
This is something that Connor and I have talked about quite a bit over the
last couple of months. The core idea is to replace NIR's current 32-bit
0/-1 D3D10-style booleans with a 1-bit data type. All in all, I think it
worked out pretty well though I really don't like the proliferation of
32-bit
On 10/22/18 10:34 AM, Matt Turner wrote:
> On Fri, Oct 5, 2018 at 11:15 AM Sagar Ghuge wrote:
>>
>> avoid misinterpretation of encoded immediate values in instruction and
>> disassembled output.
>>
>> Signed-off-by: Sagar Ghuge
>> ---
>> While encoding the immediate floating point values in ins
On Mon, Sep 24, 2018 at 4:20 AM Tapani Pälli wrote:
>
> From: Scott D Phillips
>
> Rename the (un)map_gtt functions to (un)map_map (map by
> returning a map) and add new functions (un)map_tiled_memcpy that
> return a shadow buffer populated with the intel_tiled_memcpy
> functions.
>
> Tiling/deti
On Monday, October 22, 2018 2:57:10 AM PDT Lionel Landwerlin wrote:
> Could you maybe update src/intel/tools/aubinator_viewer_decoder.cpp
> (function handle_state_base_address) ?
>
> Either way :
>
> Reviewed-by: Lionel Landwerlin
Oops, good call, thanks!
Pushed a v2 that updates both.
sign
On 10/22/18 10:14 AM, Matt Turner wrote:
> On Tue, Oct 16, 2018 at 4:57 PM Sagar Ghuge wrote:
>>
>
> Let's describe a little of why we're doing this and how we found it.
> If I recall correctly, we set a NOP (XYZW) swizzle on 3-src
> instructions, except we set an swizzle on LRP. Is that c
And pushed, thanks!
Quoting Matt Turner (2018-10-22 10:40:36)
> Thanks Dylan!
>
> Reviewed-by: Matt Turner
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https://bugs.freedesktop.org/show_bug.cgi?id=108508
--- Comment #5 from Alex Deucher ---
(In reply to Ahmed Elsayed from comment #4)
> I am sorry. You mean mesa-dev@lists.freedesktop.org ?
Correct.
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Thanks Dylan!
Reviewed-by: Matt Turner
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On Fri, Oct 5, 2018 at 11:15 AM Sagar Ghuge wrote:
>
> avoid misinterpretation of encoded immediate values in instruction and
> disassembled output.
>
> Signed-off-by: Sagar Ghuge
> ---
> While encoding the immediate floating point values in instruction we use
> values upto precision 8, but while
On Tue, Oct 16, 2018 at 4:57 PM Sagar Ghuge wrote:
>
Let's describe a little of why we're doing this and how we found it.
If I recall correctly, we set a NOP (XYZW) swizzle on 3-src
instructions, except we set an swizzle on LRP. Is that correct?
> Signed-off-by: Sagar Ghuge
> ---
> src/in
On Mon, Oct 22, 2018 at 12:10 PM Emil Velikov
wrote:
> From: Emil Velikov
>
> On older kernels, the drmGetDevice() call will wake up all the GPUs
> on the system, while fetching the PCI revision.
>
> Use the 2 version of the API and pass flags == 0, so we don't fetch the
> device PCI revision, s
From: Emil Velikov
On older kernels, the drmGetDevice() call will wake up all the GPUs
on the system, while fetching the PCI revision.
Use the 2 version of the API and pass flags == 0, so we don't fetch the
device PCI revision, since we don't need that information.
Fixes: baa38c144f6 ("vulkan/w
On Mon, Oct 22, 2018 at 9:53 AM Sagar Ghuge wrote:
>
> Thank you for reviewing the patch.
>
> On 10/22/18 5:02 AM, Samuel Iglesias Gonsálvez wrote:
> >
> >
> > On 20/10/18 3:25, Sagar Ghuge wrote:
> >> To have uniform behavior while disassembling send(c) instruction use
> >> register type of unsig
Thank you for reviewing the patch.
On 10/22/18 5:02 AM, Samuel Iglesias Gonsálvez wrote:
>
>
> On 20/10/18 3:25, Sagar Ghuge wrote:
>> To have uniform behavior while disassembling send(c) instruction use
>> register type of unsigned doubleword for src1 when message descriptor is
>> immediate va
Re: The list.
It doesn't always happen every month, but I've seen it multiple times now,
as far back as January 2018, though possibly earlier.
The gzip mail archive however has all the messages that are missing from
the web archive.
https://lists.freedesktop.org/archives/mesa-dev/2018-October.txt
Okay, I'll just leave it as "auto-off" on windows for now, with the toggle to
explicitly turn it on if someone has a use case for that.
Thanks,
Dylan
Quoting Jose Fonseca (2018-10-19 14:44:49)
> > Jose, does it make more sense to just make gles on windows an error in
> >meson?
>
>
> I don't mi
r600 doesn't have a hard requirement on LLVM, and therefore doesn't have
a hard requirement on libelf. Currently the logic doesn't allow that
however.
Distro-bug: https://bugs.gentoo.org/669058
Fixes: 5060c51b6f4dfb0d5358bde6523285163d3faaad
("meson: build r600 driver")
---
meson.build | 1
Fixes: 593996bc02 ("radv: implement buffer to image operations for R32G32B32")
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_bufimage.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_bufimage.c
b/src/amd/vulkan/radv_meta_bufimage.c
https://bugs.freedesktop.org/show_bug.cgi?id=107865
Alok Hota changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
Yeah... Bas said he had the same problem. The series can be found on my
wip/nir-const-src branch of you want to see it that way. I can also resend
if it's helpful.
--Jason
On October 22, 2018 06:31:01 Samuel Iglesias Gonsálvez
wrote:
Patch 7/9 has never arrived my inbox and checking the a
---
src/compiler/glsl/gl_nir_linker.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/compiler/glsl/gl_nir_linker.c
b/src/compiler/glsl/gl_nir_linker.c
index 547549bc4e0..138a12e532d 100644
--- a/src/compiler/glsl/gl_nir_linker.c
+++ b/src/compiler/glsl/gl_nir_linker.c
@@
When using a SPIR-V shader. Note that needs to be done before linking
uniforms, so when creating the uniform storage entries, block_index
could be filled properly (among other things).
---
src/mesa/drivers/dri/i965/brw_link.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drive
Since ARB_gl_spirv it is possible to miss a lot of name reflection
information, so it is needed to add NULL name checks for several
queries, and return a specific value on those cases. This commit add
them for ACTIVE_UNIFORM_BLOCK_MAX_NAME_LENGTH,
ACTIVE_ATTRIBUTE_MAX_LENGTH and ACTIVE_UNIFORM_MAX_
This can happens if we are running an SPIR-V shader (ARB_gl_spirv).
---
src/mesa/main/shader_query.cpp | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index 11ecd71c575..b775b4231c2
From: Antia Puentes
---
src/compiler/glsl/gl_nir_linker.c | 79 +++
1 file changed, 79 insertions(+)
diff --git a/src/compiler/glsl/gl_nir_linker.c
b/src/compiler/glsl/gl_nir_linker.c
index 138a12e532d..acec0fe1f03 100644
--- a/src/compiler/glsl/gl_nir_linke
The function had a mix of true/GL_TRUE and false/GL_FALSE
returns. Using GL_TRUE/GL_FALSE as the function returns a GLboolean.
---
src/mesa/drivers/dri/i965/brw_link.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
b/src/mesa/dri
Until now, we were using the uniform explicit location to check if the
current nir variable already was processed, and entries on the uniform
storage added. But for UBOs/SSBOs, entries are added but we lack a
explicit location.
For those we need to rely on the UBO/SSBO binding (to the nir variable
Specifically, offset, array_stride, matrix_stride and row_major.
On GLSL, most of that info is computed, but on ARB_gl_spirv they are
explicit, and for Mesa, included on the glsl_type.
From ARB_gl_spirv spec:
"Mapping of layouts
std140/std430 -> explicit *Offset*, *ArrayStride*, and
From: Antia Puentes
Binding comparison is used to determine the block the uniform is part
of. To do the binding comparison we need the information in
UniformBlocks[] and ShaderStorageBlocks[] to be available, so we have
to call gl_nir_link_uniform_blocks() before linking the uniforms.
---
src/co
For this interfaces, the inner members are added only once as uniforms
or resources, in opposite to other cases, like a uniform array of
structs.
For those guessing why a issue (16) from ARB_program_interface_query
was used, instead of a quote of the core spec: The core spec is not
really clear ab
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