From: Dave Airlie
If GLSL has already done the lowering, we'd rather not crash in this pass.
Reviewed-by: Kenneth Graunke
---
src/compiler/nir/nir_lower_clip_cull_distance_arrays.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/compiler/nir/nir_lower_clip_cull_distance_arrays.c
GL exposes separate queries for each pipeline statistics counter.
For some reason, Gallium chose to map them all to a single target,
PIPE_QUERY_PIPELINE_STATISTICS. Radeon hardware appears to query
them all as a group. pipe->get_query_result_resource() takes an
index, indicating which to write to
Hi,
On 13/10/2018 14:57, Samuel Pitoiset wrote:
Hi,
This series implements VK_EXT_transform_feedback for RADV. We tested it
quite a lot with DXVK and also with RenderDoc, it should be stable enough.
Please review, thanks!
on Tonga, this series is:
Tested-by: Andre Heider
On wine/dxvk/witc
Just in case you missed my Rb the first time you sent this patch:
Reviewed-by: Alejandro Piñeiro
On 13/10/18 15:09, Jason Ekstrand wrote:
> This is different from the GL_ARB_spirv pass because it generates a much
> simpler data structure that isn't tied to OpenGL and mtypes.h.
> ---
> src/comp
We don't need weak references to instance entrypoints because we never
have more than one of each so we don't need the NULL fall-back. This
also helps us avoid forgetting things because we now get link errors for
missing instance entrypoints.
---
src/intel/vulkan/anv_entrypoints_gen.py | 13 -
Not really sure what we're supposed to do with this one but we should do
something.
---
src/intel/vulkan/anv_wsi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 5ed1d711689..4f3f3fc57af 100644
--- a/src/intel/vulkan/a
Instead of having weak references to the anv functions and separate
trampoline functions with their own dispatch table, just make the
trampoline functions weak. This gets rid of a dispatch table and
potentially lets the compiler delete the unused weak function. The
end result is a reduction in th
Yeah
This is where things get interesting. Do you know where the MOVs are
coming from? Any scalar 64-bit SSA MOVs with scalar sources I would expect
to get deleted by copy propagation. We could still get some from phis but
the right thing to do there is likely to have a 64-bit phi lowering
Reviewed-by: Jason Ekstrand
On Sun, Oct 14, 2018 at 5:12 PM Matt Turner wrote:
> ---
> src/intel/compiler/brw_fs.cpp | 6 ++
> src/intel/compiler/brw_shader.h | 2 ++
> 2 files changed, 8 insertions(+)
>
> diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
> index
On Sun, Oct 14, 2018 at 5:12 PM Matt Turner wrote:
> ---
> src/compiler/nir/nir.h | 1 +
> src/compiler/nir/nir_lower_int64.c | 142
> +
> 2 files changed, 143 insertions(+)
>
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index
From: Dave Airlie
The bitmap lowering code references a sampler that we never declare,
this fixes it by declaring the sampler.
---
src/compiler/nir/nir_lower_bitmap.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/compiler/nir/nir_lower_bitmap.c
b/src/compiler/nir/nir_low
From: Dave Airlie
The drawpixel lowering references undeclared samplers, but also
missing a texture handle.
---
src/compiler/nir/nir_lower_drawpixels.c | 20
1 file changed, 20 insertions(+)
diff --git a/src/compiler/nir/nir_lower_drawpixels.c
b/src/compiler/nir/nir_lower_
On October 14, 2018 17:12:34 Matt Turner wrote:
From: Jason Ekstrand
[mattst88]: Found in an old branch of Jason's.
Jason implemented: inot, iand, ior, iadd, isub, ineg, iabs, compare,
imin, imax, umin, umax
Matt implemented: ixor, imov, bcsel
---
src/compiler/nir/nir_lowe
FINISHME: Figure out what to do about lowering mov operations. Currently
if we attempt to lower them in NIR we get stuck in an infinite loop. The
last patch of this series lowers them in the backend instead, but I'm
certainly open to ideas.
---
src/compiler/nir/nir.h | 9 +++-
src/com
Unfortunately some int64 lowerings generate more int64 operations, so we
need to call this function a few times. Also call
nir_lower_alu_to_scalar() beforehand to make more int64 operations
available for lowering.
---
src/intel/compiler/brw_nir.c | 10 +++---
1 file changed, 7 insertions(+), 3
---
src/intel/compiler/brw_nir.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 066724c58a6..7eb9c385694 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -677,9 +67
---
src/compiler/nir/nir.h | 1 +
src/compiler/nir/nir_lower_int64.c | 142 +
2 files changed, 143 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 12cbd030e21..2c477126acc 100644
--- a/src/compiler/nir/nir.h
+++ b/
FINISHME: Lower them in NIR instead?
---
src/intel/compiler/brw_fs.cpp | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 69726ed70e8..9e50df59356 100644
--- a/src/intel/compiler/brw_fs.cpp
+
From: Jason Ekstrand
[mattst88]: Found in an old branch of Jason's.
Jason implemented: inot, iand, ior, iadd, isub, ineg, iabs, compare,
imin, imax, umin, umax
Matt implemented: ixor, imov, bcsel
---
src/compiler/nir/nir_lower_int64.c | 186 ++
---
src/intel/compiler/brw_fs.cpp | 6 ++
src/intel/compiler/brw_shader.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 23a25fedca5..69726ed70e8 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/br
What happened to v2?
On 13/10/18 11:57 pm, Samuel Pitoiset wrote:
We shouldn't try to compact any varyings known as always
active IO, especially XFB outputs. For example, if one
component of an xfb output is also used as input varying
in the next stage, it shouldn't be compacted.
Because we loo
For xfb in glsl we just set always_active_io for varyings on each side
of the interface which should avoid this and the linking problems from
the two patches before this.
Trying to lower/split xfb varyings just seems like asking for trouble, I
suggested Samuel create a linking helper to set al
Nice!
Reviewed-by: Lionel Landwerlin
On 13/10/2018 19:35, Jason Ekstrand wrote:
There's no reason why we need generate trampoline functions for instance
functions or carry N copies of the instance dispatch table around for
every hardware generation. Splitting the tables and being more
conserv
Here I was reveling in the triviality of my fixed-pci-path implementation
and you had to show me up by implementing it properly. :-P
Implementing it properly is a better plan because we know discrete is coming.
Reviewed-by: Jason Ekstrand
On October 14, 2018 07:12:58 Lionel Landwerlin
wrote
Even though the Intel GPU are always at the same PCI location, all the
info we need is already provided by libdrm. Let's be future proof.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_device.c | 24 +++-
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vu
Acked-by: Lionel Landwerlin
On 13/10/2018 16:00, Jason Ekstrand wrote:
These were missing in the last couple of spec updates.
---
include/vulkan/vulkan.h | 4 +++
include/vulkan/vulkan_fuchsia.h | 58 +
2 files changed, 62 insertions(+)
create mode
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