https://bugs.freedesktop.org/show_bug.cgi?id=104988
Bug ID: 104988
Summary: Please do a mesa-demos/mesa-utils release. The last
one was 2 years ago.
Product: Mesa
Version: unspecified
Hardware: Other
OS: All
Reviewed-by: Tapani Pälli
On 06.02.2018 19:06, Lionel Landwerlin wrote:
This helps figuring out potential problems when metrics don't show up
on frameretrace for example.
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 2 ++
1 file changed, 2 insert
Both patches are
Reviewed-by: Tapani Pälli
On 07.02.2018 01:56, Lionel Landwerlin wrote:
ioctl() might be interrupted, use drmIoctl() instead as it'll retry
automatically.
Fixes: 27ee83eaf7e "i965: perf: add support for userspace configurations"
Cc: "18.0"
Signed-off-by: Lionel Landwerlin
--
'indirect_params' was a bit vague. Use the names that we use in
gallium's pipe_draw_indirect_info.
---
src/mesa/state_tracker/st_draw.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/mesa/state_tracker/st_draw.c b/src/mesa/state_tracker/st_draw.c
index 2fe70
And rename a parameter name.
---
src/mesa/vbo/vbo.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/mesa/vbo/vbo.h b/src/mesa/vbo/vbo.h
index a04f9b8..d594ba8 100644
--- a/src/mesa/vbo/vbo.h
+++ b/src/mesa/vbo/vbo.h
@@ -149,9 +149,10 @@ vbo_save_EndCallList(struct
---
src/gallium/auxiliary/cso_cache/cso_context.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c
b/src/gallium/auxiliary/cso_cache/cso_context.c
index dd9821e..1b5d4b5 100644
--- a/src/gallium/auxiliary/cso_cache/cso_context.c
+++ b/src/gal
---
src/gallium/auxiliary/util/u_simple_shaders.c | 36 ++-
src/gallium/auxiliary/util/u_simple_shaders.h | 29 ++---
2 files changed, 34 insertions(+), 31 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_simple_shaders.c
b/src/gallium/auxiliary/util
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index c92b1d9..5e1674c 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
---
src/gallium/auxiliary/tgsi/tgsi_ureg.c | 24
src/gallium/auxiliary/tgsi/tgsi_ureg.h | 22 +++---
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index 5890
---
src/gallium/auxiliary/util/u_blit.c | 9 +
src/gallium/auxiliary/util/u_blit.h | 4 ++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_blit.c
b/src/gallium/auxiliary/util/u_blit.c
index 3f92476..7178e89 100644
--- a/src/gallium/auxiliary/u
---
src/gallium/auxiliary/tgsi/tgsi_ureg.c | 62 ++
src/gallium/auxiliary/tgsi/tgsi_ureg.h | 44
2 files changed, 55 insertions(+), 51 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
b/src/gallium/auxiliary/tgsi/tgsi_ureg.
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 10 ++
src/mesa/state_tracker/st_glsl_to_tgsi.h | 3 ++-
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 5e1674c..39a81fa 100644
Just a few nit-picks below...
On 02/06/2018 09:20 PM, srol...@vmware.com wrote:
From: Roland Scheidegger
We need this to handle some oddball dx10 format
(DXGI_FORMAT_R10G10B10_XR_BIAS_A2_UNORM). What you can do with this
format is very limited, hence we don't want to add it as a gallium
format
On 02/06/2018 09:20 PM, srol...@vmware.com wrote:
From: Roland Scheidegger
The writemask handling was busted, since writing defaults to output
meant they got overwritten by the tex sampling anyway. Albeit the
affected components were undefined, so maybe with some luck it
still would have worked
From: Roland Scheidegger
We need this to handle some oddball dx10 format
(DXGI_FORMAT_R10G10B10_XR_BIAS_A2_UNORM). What you can do with this
format is very limited, hence we don't want to add it as a gallium
format (we could not express the properties of this format as
ordinary format properties
From: Roland Scheidegger
The writemask handling was busted, since writing defaults to output
meant they got overwritten by the tex sampling anyway. Albeit the
affected components were undefined, so maybe with some luck it
still would have worked with some drivers - if not could as well
kill it...
https://bugs.freedesktop.org/show_bug.cgi?id=104983
Bug ID: 104983
Summary: current version, warning during make process in glsl
Product: Mesa
Version: unspecified
Hardware: ARM
OS: Linux (All)
Status: NEW
On Tue, Feb 6, 2018 at 5:09 PM, Nanley Chery wrote:
> On Mon, Feb 05, 2018 at 06:16:26PM -0800, Jason Ekstrand wrote:
> > This commit completely reworks aux tracking. This includes a number of
> > somewhat distinct changes:
> >
> > 1) Since we are no longer fast-clearing multiple slices, we onl
On Fri, 2018-02-02 at 10:22 +0100, Pierre Moreau wrote:
> On 2018-02-02 — 18:07, Timothy Arceri wrote:
> >
> >
> > On 02/02/18 17:21, Timothy Arceri wrote:
> > > On 02/02/18 16:38, Jan Vesely wrote:
> > > > On Fri, 2018-02-02 at 15:03 +1100, Timothy Arceri wrote:
> > > > > When PIPE_SHADER_IR_LLV
The select fds have to be reinitialized before each call to select.
Signed-off-by: Ilia Mirkin
---
drm-legacy.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drm-legacy.c b/drm-legacy.c
index a0b419a..fd98a38 100644
--- a/drm-legacy.c
+++ b/drm-legacy.c
@@ -53,10
Commit bit in the message descriptor (Bit 13) must be always set
to true in CNL+ for memory fence messages. It also fixes a piglit
GPU hang on cnl+ in simulation environment.
Piglit test: arb_shader_image_load_store-shader-mem-barrier
See HSD ES # 1404612949
Signed-off-by: Anuj Phogat
Cc: mesa-st
From Message Descriptor section in gfxspecs:
"Memory fence messages without Commit Enable set do not return
anything to the thread (response length is 0 and destination
register is null)."
It fixes a piglit GPU hang in simulation environment.
Piglit test: arb_shader_image_load_store-shader-me
On Mon, Feb 05, 2018 at 06:16:26PM -0800, Jason Ekstrand wrote:
> This commit completely reworks aux tracking. This includes a number of
> somewhat distinct changes:
>
> 1) Since we are no longer fast-clearing multiple slices, we only need
> to track one fast clear color and one fast clear t
On Tue, Feb 6, 2018 at 4:22 PM, Nanley Chery wrote:
> On Mon, Feb 05, 2018 at 04:07:19PM -0800, Anuj Phogat wrote:
> > I don't have a test case hitting this assert. But, it's nice to have
> > an assert checking the limit.
> >
> > Signed-off-by: Anuj Phogat
> > ---
> > src/intel/isl/isl_surface_
On Mon, Feb 05, 2018 at 04:08:40PM -0800, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/genX_state_upload.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
> b/src/mesa/drivers/dri/i965/
From: Kevin Rogovin
Adds a new debug tool to pad each GEM BO allocated with (weak)
pseudo-random noise values which are then checked after each
batchbuffer dispatch to the kernel. This can be quite valuable to
find diffucult to track down heisenberg style bugs.
[scott.d.phill...@intel.com: split
This breaks nouveau (at least on nv50). Same deal as in commit
2b938a390c15a06be8cf706083890c822979508f which fixed a similar issue
where this assumption that buffer doesn't need sampler was also
temporarily introduced.
Do I need to go change a ton of stuff in nouveau, or can we stick with
the ori
On Mon, Feb 05, 2018 at 04:07:19PM -0800, Anuj Phogat wrote:
> I don't have a test case hitting this assert. But, it's nice to have
> an assert checking the limit.
>
> Signed-off-by: Anuj Phogat
> ---
> src/intel/isl/isl_surface_state.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a
ioctl() might be interrupted, use drmIoctl() instead as it'll retry
automatically.
Fixes: 27ee83eaf7e "i965: perf: add support for userspace configurations"
Cc: "18.0"
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 4 ++--
1 file changed, 2 insertions(+
The initial revision of the patch adding loadable configs was testing
the feature's availability by adding a new config successfully and
then removing it.
A second version tested the availability just by exercising the
removal. But some unused code remained.
Signed-off-by: Lionel Landwerlin
---
Quoting Dylan Baker (2018-02-06 15:19:48)
> Quoting kallisti5 (2018-02-05 20:24:20)
> > On 2018-02-05 18:13, Dylan Baker wrote:
> > >
> > > Pretty close. I lied, apparently the pthreads fix is in 0.44
> > >
> > > https://github.com/mesonbuild/meson/commit/fc547ad05e5a8e650ae5bc2ecc7d40e4dbcc9f0f
Quoting kallisti5 (2018-02-05 20:24:20)
> On 2018-02-05 18:13, Dylan Baker wrote:
> >
> > Pretty close. I lied, apparently the pthreads fix is in 0.44
> >
> > https://github.com/mesonbuild/meson/commit/fc547ad05e5a8e650ae5bc2ecc7d40e4dbcc9f0f
> >
> > Here's my branch, but it needs rebase pretty
You probably want to add new ST_PIPELINE_xxx. See how state filtering
works with ST_PIPELINE_CLEAR.
Marek
On Tue, Feb 6, 2018 at 9:18 PM, wrote:
> From: Mathias Fröhlich
>
> Hi Brian,
>
> I think you are right the _mesa_set_drawing_arrays better belong into
> the state tracker. You mean like t
On Tue, Feb 6, 2018 at 9:05 PM, James Zhu wrote:
> Based on amdgpu hardware query information to check if UVD hevc enc support
>
> Signed-off-by: James Zhu
> ---
> src/amd/common/ac_gpu_info.c | 10 +-
> src/amd/common/ac_gpu_info.h | 1 +
> 2 files changed, 10 insertions(+), 1 deletion
I like that,
Reviewed-By: Gert Wollny
Am Mittwoch, den 07.02.2018, 06:25 +1000 schrieb Dave Airlie:
> From: Glenn Kennard
>
> This is taken from Glenn Kennards scratch series, but separated
> out as a cleanup by me.
>
> Signed-off-by: Dave Airlie
> ---
> src/gallium/drivers/r600/r600_shader
Ported from RadeonSI.
Only one F1 2017 shader is affected, code size decreased
from 532 to 488 on both Polaris10 and Vega10.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 146 +---
1 file changed, 47 insertions(+), 99 deletions(-)
diff
From: Glenn Kennard
This is taken from Glenn Kennards scratch series, but separated
out as a cleanup by me.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 37 --
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/src/gallium
From: Mathias Fröhlich
Hi Brian,
I think you are right the _mesa_set_drawing_arrays better belong into
the state tracker. You mean like the below?
I added also two other callbacks that lookes suspicious to me.
I just sent the single patch in question out of the series of three.
Tested with pigli
Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode
On 2018-02-05 04:12 PM, Boyuan Zhang wrote:
On 2018-02-05 12:16 PM, James Zhu wrote:
Signed-off-by: James Zhu
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/s
Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode
On 2018-02-06 11:13 AM, Boyuan Zhang wrote:
this patch is Reviewed-by: Boyuan Zhang
On 2018-02-05 12:16 PM, James Zhu wrote:
Enable UVD encode for HEVC main profile
Signed-off-by: James Zhu
---
src/gallium/drivers/
Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode
On 2018-02-05 02:30 PM, James Zhu wrote:
On 2018-02-05 01:04 PM, Alex Deucher wrote:
On Mon, Feb 5, 2018 at 12:16 PM, James Zhu wrote:
Implement UVD hevc encode functions
Signed-off-by: James Zhu
---
1
Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode
On 2018-02-06 10:27 AM, Boyuan Zhang wrote:
On 2018-02-05 02:41 PM, James Zhu wrote:
Implement UVD hevc encode functions
Signed-off-by: James Zhu
---
src/gallium/drivers/radeon/radeon_uvd_enc.c | 340
++
Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode
On 2018-02-05 03:25 PM, Boyuan Zhang wrote:
On 2018-02-05 12:16 PM, James Zhu wrote:
Add UVD hevc encode pipe video codec creation entry
Signed-off-by: James Zhu
---
src/gallium/drivers/radeonsi/si_uvd.c | 13 ++
Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode
On 2018-02-06 08:56 AM, Leo Liu wrote:
General comments:
1. The patch title: please refer to previous commits under the directory,
https://cgit.freedesktop.org/mesa/mesa/log/src/gallium/drivers/radeon
Normally either "r
Signed-off-by: James Zhu
---
src/gallium/drivers/radeon/Makefile.sources | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/gallium/drivers/radeon/Makefile.sources
b/src/gallium/drivers/radeon/Makefile.sources
index b756d72..f8ee860 100644
--- a/src/gallium/drivers/radeon/Makefile.source
Enable UVD encode for HEVC main profile
Signed-off-by: James Zhu
---
src/gallium/drivers/radeonsi/si_get.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_get.c
b/src/gallium/drivers/radeonsi/si_get.c
index 8002362..64f76b4 100644
--- a/src
Support UVD HEVC encode in amdgpu cs
Signed-off-by: James Zhu
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 1927a3a..92d5394 100644
--- a/src/gal
The whole series are the updated version. Changes are made mainly based
on the comments from prevous code review from Alex, Leo and Boyuan
James Zhu (8):
amd/common:add uvd hevc enc support check in hw query
winsys/amdgpu:add uvd hevc enc support in amdgpu cs
radeon/uvd:add uvd hevc enc hw
Add hevc encode hardware interface for UVD
Signed-off-by: James Zhu
---
src/gallium/drivers/radeon/radeon_uvd_enc.h | 471
1 file changed, 471 insertions(+)
create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h
diff --git a/src/gallium/drivers/radeon/radeo
Implement required IBs for UVD HEVC encode.
Signed-off-by: James Zhu
---
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1115 +++
1 file changed, 1115 insertions(+)
create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
diff --git a/src/gallium/drivers/radeon
Based on amdgpu hardware query information to check if UVD hevc enc support
Signed-off-by: James Zhu
---
src/amd/common/ac_gpu_info.c | 10 +-
src/amd/common/ac_gpu_info.h | 1 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common
Add UVD hevc encode pipe video codec creation entry
Signed-off-by: James Zhu
---
src/gallium/drivers/radeonsi/si_uvd.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_uvd.c
b/src/gallium/drivers/radeonsi/si_uvd.c
index 64f2f8e
Implement UVD hevc encode functions
Signed-off-by: James Zhu
---
src/gallium/drivers/radeon/radeon_uvd_enc.c | 370
1 file changed, 370 insertions(+)
create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c
diff --git a/src/gallium/drivers/radeon/radeon_uvd_e
https://bugs.freedesktop.org/show_bug.cgi?id=94194
Martin Peres changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=94194
--- Comment #7 from Kenneth Graunke ---
Pam has a number of solid contributions to i965 now, I'd be in favor of
granting her commit access.
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the
From: Dave Airlie
RX550 fails
dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_2
So increase the range of the workaround.
Fixes: f4c534ef6 (radv: don't enable tc compat for d32s8 + 4/8 samples (v1.1))
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_image.c | 4 ++--
SWR is OK with moving to LLVM 4.0 and above.
Just to clarify: This goes to master, which means mesa 18.0 is not affected,
just 18.1 and later. Correct?
Thanks,
George
> On Feb 6, 2018, at 11:07 AM, Kyriazis, George
> wrote:
>
> As far as SWR is concerned, we’ll have to ask our customers.
Reviewed-by: Marek Olšák
Marek
On Tue, Feb 6, 2018 at 5:58 AM, Timothy Arceri wrote:
> ---
> src/amd/common/ac_llvm_build.c | 19 +++
> src/amd/common/ac_llvm_build.h | 3 +++
> src/amd/common/ac_nir_to_llvm.c | 34 --
> 3 files changed, 30 in
You don't need this helper. You can just use LLVMBuildTrunc.
Marek
On Tue, Feb 6, 2018 at 5:58 AM, Timothy Arceri wrote:
> This will be used in the following commits.
> ---
> src/amd/common/ac_llvm_build.c | 8
> src/amd/common/ac_llvm_build.h | 3 +++
> src/amd/common/ac_nir_to_llvm
For the series:
Reviewed-by: Marek Olšák
Marek
On Mon, Feb 5, 2018 at 6:22 PM, Brian Paul wrote:
> ---
> src/mesa/state_tracker/st_cb_fbo.c | 18 +-
> src/mesa/state_tracker/st_cb_texture.c | 17 -
> 2 files changed, 17 insertions(+), 18 deletions(-)
>
> di
Pushed, thanks!
Marek
On Sun, Feb 4, 2018 at 8:24 PM, Michal Navratil wrote:
> Fix INVALID_OPERATION caused by BufferData with target
> EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD when the buffer size is
> not page aligned.
> ---
> src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 11 +++
> 1 file cha
2018-02-06 17:19 GMT+02:00 Brian Paul :
> On 02/06/2018 06:48 AM, Vlad Golovkin wrote:
>>
>> Clang defines __GNUC__ macro, so one doesn't need to check __clang__
>> macro in this particular case.
>>
>> v2: added comment as per Brian Paul's suggestion
>> ---
>> src/util/macros.h | 3 ++-
>> 1 fil
On Thursday, January 25, 2018 3:29:01 AM PST Emil Velikov wrote:
> On 18 January 2018 at 07:36, Kenneth Graunke wrote:
> > Growing the batch/state buffer is a lot more dangerous than I thought.
> >
> > A number of places emit multiple state buffer sections, and then write
> > data to the returned
Reviewed-by: Marek Olšák
Marek
On Sun, Feb 4, 2018 at 8:09 PM, Ilia Mirkin wrote:
> In the case of NVIDIA hardware, ABGR is displayable but ARGB is not.
> Only advertise the one set in the visuals list.
>
> Signed-off-by: Ilia Mirkin
> ---
>
> Not sure if this is the right thing, esp for a PRI
Reviewed-by: Marek Olšák
Marek
On Sat, Feb 3, 2018 at 11:19 PM, Grazvydas Ignotas wrote:
> I hope the actual dropping of MSB is ok, but that's what's already
> happened before this change.
> ---
> src/gallium/drivers/radeonsi/si_descriptors.c | 18 --
> 1 file changed, 12 inser
Reviewed-by: Marek Olšák
Marek
On Sat, Feb 3, 2018 at 11:19 PM, Grazvydas Ignotas wrote:
> It seems these were missed when struct pipe_context * argument was
> added to hud_graph::query_new_value.
>
> Fixes: 3132afdf4c "gallium/hud: pass pipe_context explicitly to most
> functions"
> ---
> sr
For the series:
Reviewed-by: Marek Olšák
Marek
On Fri, Feb 2, 2018 at 7:08 AM, Timothy Arceri wrote:
> We move the nir check before the shader cache call so that we can
> call a nir based caching function in a following patch.
>
> Also with this change we simply check if vertex shaders support
On 02/06/2018 09:32 AM, Vadym Shovkoplias wrote:
From: Vadym Shovkoplias
Add support for GL_NUM_SHADING_LANGUAGE_VERSIONS
and glGetStringi for GL_SHADING_LANGUAGE_VERSION
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104915
Signed-off-by: Andriy Khulap
Signed-off-by: Vadym Shovkoplia
On Tue, Feb 6, 2018 at 1:37 PM, Eric Engestrom
wrote:
> On Sunday, 2018-02-04 00:19:33 +0200, Grazvydas Ignotas wrote:
>> At least with vim, this is needed to actually get tab instead of
>> 3 spaces after hitting the tab key.
>
> Are you sure?
For my copy of vim (7.4.1689) yes. Not sure what vers
On Tuesday, 2018-02-06 09:59:32 -0700, Brian Paul wrote:
> Instead of testing for formats==NULL everywhere, just point formats at
> a dummy array which will be discarded.
> ---
> src/mesa/main/texcompress.c | 200
> ++--
> 1 file changed, 83 insertions(+),
As far as SWR is concerned, we’ll have to ask our customers. Will respond
shortly.
Thanks,
George
> On Feb 6, 2018, at 9:42 AM, Andres Gomez wrote:
>
> Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
> Cc: Marek Olšák
> Cc: Emil Velikov
> Cc: Jan Vesely
> Signed-off-by: Andres Gom
This helps figuring out potential problems when metrics don't show up
on frameretrace for example.
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
b/src
I made a comment on patch 1. With that addressed, the series is:
Reviewed-by: Marek Olšák
Marek
On Fri, Feb 2, 2018 at 5:03 AM, Timothy Arceri wrote:
> When PIPE_SHADER_IR_LLVM existed this query made sense but now it
> always returns PIPE_SHADER_IR_NATIVE. Also it is now conlicting
> with PIP
---
src/mesa/main/texcompress.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 1cc13a5..1c128e4 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -361,25 +3
Instead of testing for formats==NULL everywhere, just point formats at
a dummy array which will be discarded.
---
src/mesa/main/texcompress.c | 200 ++--
1 file changed, 83 insertions(+), 117 deletions(-)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/
On Fri, Feb 2, 2018 at 8:07 AM, Timothy Arceri wrote:
>
>
> On 02/02/18 17:21, Timothy Arceri wrote:
>>
>> On 02/02/18 16:38, Jan Vesely wrote:
>>>
>>> On Fri, 2018-02-02 at 15:03 +1100, Timothy Arceri wrote:
When PIPE_SHADER_IR_LLVM existed this query made sense but now it
always r
On Tue, 2018-02-06 at 11:01 -0500, Jan Vesely wrote:
> On Tue, 2018-02-06 at 17:42 +0200, Andres Gomez wrote:
> > Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
> > Cc: Marek Olšák
> > Cc: Emil Velikov
> > Cc: Jan Vesely
> > Signed-off-by: Andres Gomez
> > ---
> >
[...]
> > @@ -131,
From: Vadym Shovkoplias
Add support for GL_NUM_SHADING_LANGUAGE_VERSIONS
and glGetStringi for GL_SHADING_LANGUAGE_VERSION
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104915
Signed-off-by: Andriy Khulap
Signed-off-by: Vadym Shovkoplias
---
src/mapi/glapi/gen/GL4x.xml | 1 +
sr
this patch is Reviewed-by: Boyuan Zhang
On 2018-02-05 12:16 PM, James Zhu wrote:
Enable UVD encode for HEVC main profile
Signed-off-by: James Zhu
---
src/gallium/drivers/radeonsi/si_get.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/s
On Tue, 2018-02-06 at 17:42 +0200, Andres Gomez wrote:
> Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
> Cc: Marek Olšák
> Cc: Emil Velikov
> Cc: Jan Vesely
> Signed-off-by: Andres Gomez
> ---
>
> Additionally, AMD's support removal for LLVM 3.9 has also affected the
> distcheck targ
Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
Cc: Marek Olšák
Cc: Emil Velikov
Cc: Jan Vesely
Signed-off-by: Andres Gomez
---
Additionally, AMD's support removal for LLVM 3.9 has also affected the
distcheck target.
Unfortunately, SWR distribution needs 3.9.x, therefore, we cannot
si
All three look good to me.
Reviewed-by: Brian Paul
On 02/06/2018 12:59 AM, mathias.froehl...@gmx.net wrote:
From: Mathias Fröhlich
Hi,
Simple code deduplication and factoring out a function that
will be usefull soon.
please review
thanks!!
Mathias
And use it in the enable code path.
On Fri, Feb 2, 2018 at 5:03 AM, Timothy Arceri wrote:
> ---
> src/gallium/drivers/radeonsi/si_shader_nir.c | 30
> +++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
> b/src/gallium/drivers/radeonsi/si_sha
On 2018-02-05 02:41 PM, James Zhu wrote:
Implement UVD hevc encode functions
Signed-off-by: James Zhu
---
src/gallium/drivers/radeon/radeon_uvd_enc.c | 340
1 file changed, 340 insertions(+)
create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c
diff
The name member of gralloc_handle_t is no longer needed and has been removed.
The version field has also been bumped.
Signed-off-by: Robert Foss
---
android/gralloc_handle.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
Change the gralloc_handle_t format to signify the fourcc pixel format
code instead of the Android pixel format definition.
This is desirable since the fourcc code is what is used within the DRM
subsystem. Naturally translation will still have to happen somewhere.
Also bump the gralloc_handle_t ve
This struct is used in mesa and drm_hwcomposer.
Versions of if have been implemented in several grallocs:
drm_gralloc, gbm_gralloc, minigbm and intel-minigbm.
Other than the 1:1 move of the struct a new generic name
has been chosen and variables have had comments added to them.
Signed-off-by: Rob
In order to lessen future alignment issues, lets switch to
fixed width integers where possible.
This excludes the data_owner since it is a pid_t which
in theory could be larger than 32 bits.
Signed-off-by: Robert Foss
---
android/gralloc_handle.h | 20 +++-
1 file changed, 11 in
The version variable will be used for versioning of this
struct and the corresponding accessor functions.
Signed-off-by: Robert Foss
---
android/gralloc_handle.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
index 4
Mark magic member of gralloc_handle_t as const.
Signed-off-by: Robert Foss
---
android/gralloc_handle.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
index 7cbc8ee7cef3..5d8a19ea0c2e 100644
--- a/android/gralloc_handle.h
+
This series moves {gbm,drm,cros}_gralloc_handle_t struct to libdrm,
since at least 4 implementations exist, and share a lot of contents.
The idea is to keep the common stuff defined in one place, and libdrm
is the common codebase to all of these platforms.
Additionally, having this struct defined
On 02/06/2018 06:48 AM, Vlad Golovkin wrote:
Clang defines __GNUC__ macro, so one doesn't need to check __clang__
macro in this particular case.
v2: added comment as per Brian Paul's suggestion
---
src/util/macros.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/uti
On 02/06/2018 01:08 AM, Rob Herring wrote:
On Mon, Jan 29, 2018 at 11:37 AM, Robert Foss wrote:
This struct is used in mesa and drm_hwcomposer.
Versions of if have been implemented in several grallocs:
drm_gralloc, gbm_gralloc, minigbm and intel-minigbm.
Other than the 1:1 move of the struct
Reviewed-by: Marek Olšák
Marek
On Tue, Feb 6, 2018 at 1:11 AM, Timothy Arceri wrote:
> This fixes a regression for now, in the future we should gather
> the used components properly.
>
> V2: just set for VS and correctly handle doubles
>
> Fixes: be973ed21f6e "radeonsi: load the right number o
Fixes: d50937f137 "vulkan/wsi: Implement prime in a completely generic way"
---
src/vulkan/wsi/wsi_common.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/vulkan/wsi/wsi_common.c b/src/vulkan/wsi/wsi_common.c
index e9e43e1204..90ed07b785 100644
--- a/src/vulkan/wsi/wsi_
General comments:
1. The patch title: please refer to previous commits under the directory,
https://cgit.freedesktop.org/mesa/mesa/log/src/gallium/drivers/radeon
Normally either "radeon/uvd" or "radeonsi"
Applies to changes on other directory.
2. Code style and indentation refer to:
https://
Clang defines __GNUC__ macro, so one doesn't need to check __clang__
macro in this particular case.
v2: added comment as per Brian Paul's suggestion
---
src/util/macros.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/util/macros.h b/src/util/macros.h
index 432d513930..
https://bugs.freedesktop.org/show_bug.cgi?id=104949
--- Comment #8 from Eric Engestrom ---
(In reply to Wayne Blaszczyk from comment #7)
> I don't have eglinfo. What package does that come from?
it's in mesa-demos, but it's not necessarily provided by a package in your
distro (I think ubuntu doe
https://bugs.freedesktop.org/show_bug.cgi?id=104949
--- Comment #7 from Wayne Blaszczyk ---
(In reply to Eric Engestrom from comment #6)
> (In reply to Wayne Blaszczyk from comment #5)
> > es2_info does not return EGL_WL_bind_wayland_display either before or after
> > the patch, if that is what y
https://bugs.freedesktop.org/show_bug.cgi?id=104949
--- Comment #6 from Eric Engestrom ---
(In reply to Wayne Blaszczyk from comment #5)
> es2_info does not return EGL_WL_bind_wayland_display either before or after
> the patch, if that is what you were asking for?
for egl information you'll want
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