This patch is still missing a review, any takers? This is required to
pass one of the SPIR-V CTS tests.
Iago
On Thu, 2017-11-16 at 08:53 +0100, Iago Toral Quiroga wrote:
> We currently handle this by lowering it to a uniform for gen8+ but
> the SPIR-V path generates this as a system value, so han
From: Dave Airlie
On cayman it appears the cmp component is now in Z.
Fixes:
arb_shader_image_load_store-dead-fragments on cayman.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drive
Hello Christian,
On Sat, Nov 25, 2017 at 05:10:36PM +0100, Christian Gmeiner wrote:
> 2017-11-18 10:44 GMT+01:00 Wladimir J. van der Laan :
> > Update state objects to add new state, and emit function to emit new
> > state.
> >
> > Signed-off-by: Wladimir J. van der Laan
> > Reviewed-by: Christia
Whoops subject should be st/glsl_to_tgsi fixed locally.
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Acked-by: Tapani Pälli
On 11/24/2017 04:25 PM, Emil Velikov wrote:
From: Emil Velikov
Add -fno-math-errno and -fno-trapping-math to the build.
Mesa does not depend on the functionality provided, thus this should
result in slightly faster code and smaller binaries.
Cc: Tapani Pälli
Cc: Rob
Acked-by: Tapani Pälli
On 11/24/2017 04:25 PM, Emil Velikov wrote:
From: Emil Velikov
The compiler will warns us when we're misusing undefined macros.
Note: this will trigger a bunch of warnings, which will be resolved
ASAP.
Cc: Tapani Pälli
Cc: Rob Herring
Signed-off-by: Emil Velikov
---
driver_cache_blob was introduced with the i965 disk cache, it allows
us to simplify the cache a little and possibly offers some minor
speed improvements since we load the GLSL metadata and TGSI from
disk in one pass.
Using driver_cache_blob should also make it straight forward to
implement binary
On 27/11/17 13:01, Eric Anholt wrote:
Gert Wollny writes:
Array who's elements are only accessed directly are replaced by the
according number of temporary registers. By doing so the otherwise
reserved register range becomes subject to further optimizations like
copy propagation and register m
I suspect this patch doesn't compile. I think pEntryPoint is meant to be
passed as an argument to this function.
On 16/11/17 00:22, Eduardo Lima Mitev wrote:
From: Nicolai Hähnle
v2: use gl_spirv_validation instead of spirv_to_nir.
This method just validates the shader. The conversion to
On 16/11/17 00:22, Eduardo Lima Mitev wrote:
---
src/mesa/main/glspirv.c | 51 ++---
1 file changed, 48 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c
index 86f1d221cc9..9332764f152 100644
--- a/src/mesa
Gert Wollny writes:
> Array who's elements are only accessed directly are replaced by the
> according number of temporary registers. By doing so the otherwise
> reserved register range becomes subject to further optimizations like
> copy propagation and register merging.
>
> Thanks to the resulti
Eric Engestrom writes:
> Signed-off-by: Eric Engestrom
This and the previous patch are:
Reviewed-by: Eric Anholt
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Eric Engestrom writes:
> On Wednesday, 2017-11-22 12:28:17 -0800, Eric Anholt wrote:
>> Jordan Justen writes:
>>
>> > On 2017-11-22 09:59:34, Eric Engestrom wrote:
>> >> A recent thread [1] made me check our local specs to see which ones were
>> >> upstream. This series removes the ones that ar
On 16/11/17 00:50, Eric Engestrom wrote:
On Wednesday, 2017-11-15 14:22:04 +0100, Eduardo Lima Mitev wrote:
From: Nicolai Hähnle
---
src/mapi/glapi/gen/ARB_gl_spirv.xml | 21 ++
src/mapi/glapi/gen/Makefile.am | 1 +
src/mapi/glapi/gen/gl_API.xml | 4 +++
From: Dave Airlie
This fixes hangs on cayman with
tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test
This has a single if/else in it, and when this peephole activated,
it would set the jump target to NULL if there was no instruction
after the final POP. This ad
From: Dave Airlie
This fixes hangs on cayman with
tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test
This has a single if/else in it, and when this peephole activated,
it would set the jump target to NULL if there was no instruction
after the final POP. This ad
Reviewed-by: Lionel Landwerlin
On 26/11/17 10:09, Kenneth Graunke wrote:
These were moved to src/intel/common/gen_debug.h, but they are not
common code. They assume that brw_context or gl_context variables
exist, named brw or ctx. That isn't remotely true outside of i965.
---
src/intel/comm
Reviewed-by: Lionel Landwerlin
On 26/11/17 09:27, Kenneth Graunke wrote:
We want to program the 3DSTATE_RASTER field to the gl_context value,
not the other way around.
Fixes: 13ac46557ab1 (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.)
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 2
https://bugs.freedesktop.org/show_bug.cgi?id=103921
Bug ID: 103921
Summary: llvmpipe consume all resources on GPU Vega RX (amdgpu
driver) with mesa 17.2.4 if disabled IGPU
Product: Mesa
Version: 17.2
Hardware: Other
On Sun, Nov 26, 2017 at 1:29 PM, Rob Clark wrote:
> On Sun, Nov 26, 2017 at 12:08 PM, Ilia Mirkin wrote:
>> Since this is all happening as a post-optimization fixup, and offsets
>> are generally immediates, we can just do the calculation directly.
>>
>> Signed-off-by: Ilia Mirkin
>> ---
>>
>> On
On Sun, Nov 26, 2017 at 12:08 PM, Ilia Mirkin wrote:
> Since this is all happening as a post-optimization fixup, and offsets
> are generally immediates, we can just do the calculation directly.
>
> Signed-off-by: Ilia Mirkin
> ---
>
> Only very mildly tested. Noticed it when looking closely at ou
Since this is all happening as a post-optimization fixup, and offsets
are generally immediates, we can just do the calculation directly.
Signed-off-by: Ilia Mirkin
---
Only very mildly tested. Noticed it when looking closely at our shaders,
thinking
why it tries to shift 0 by a constant. This i
Wow... Rb
On November 26, 2017 01:27:33 Kenneth Graunke wrote:
We want to program the 3DSTATE_RASTER field to the gl_context value,
not the other way around.
Fixes: 13ac46557ab1 (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.)
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
1 fi
https://bugs.freedesktop.org/show_bug.cgi?id=103668
--- Comment #7 from erhar...@mailbox.org ---
I can confirm that the test passes now. Thanks!
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https://bugs.freedesktop.org/show_bug.cgi?id=103814
almos changed:
What|Removed |Added
CC||aaalmo...@gmail.com
--- Comment #3 from almos
Quoting Kenneth Graunke (2017-11-26 10:08:49)
> This is cleaner than using a non-standard memclear macro (which does a
> memset to 0) and then initializing fields after the fact. We move the
> declarations to where we initialized the fields. While we're at it, we
> move the declaration of 'ret' t
These were moved to src/intel/common/gen_debug.h, but they are not
common code. They assume that brw_context or gl_context variables
exist, named brw or ctx. That isn't remotely true outside of i965.
---
src/intel/common/gen_debug.h| 29 -
src/mesa/drivers
This is cleaner than using a non-standard memclear macro (which does a
memset to 0) and then initializing fields after the fact. We move the
declarations to where we initialized the fields. While we're at it, we
move the declaration of 'ret' that goes with the ioctl, eliminating the
declaration s
We want to program the 3DSTATE_RASTER field to the gl_context value,
not the other way around.
Fixes: 13ac46557ab1 (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.)
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/driv
https://bugs.freedesktop.org/show_bug.cgi?id=103909
Bug ID: 103909
Summary: anv_allocator.c:113:1: error: static declaration of
‘memfd_create’ follows non-static declaration
Product: Mesa
Version: git
Hardware: x86-64 (AMD6
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