[Mesa-dev] [Bug 97549] [SNB, BXT] up to 40% perf drop from "loader/dri3: Overhaul dri3_update_num_back" commit

2016-09-04 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=97549 --- Comment #3 from Michel Dänzer --- Does the problem also occur with the modesetting driver instead of intel? If yes, I'm afraid we can't make progress on this bug without seeing at least the number of buffers used before and after my change i

Re: [Mesa-dev] [PATCH 09/10] st/vdpau: implement the new DMA-buf based interop

2016-09-04 Thread Michel Dänzer
On 05/09/16 04:37 AM, Ilia Mirkin wrote: > On Tue, Mar 8, 2016 at 7:21 AM, Christian König > wrote: >> @@ -80,7 +82,7 @@ vlVdpOutputSurfaceCreate(VdpDevice device, >> res_tmpl.depth0 = 1; >> res_tmpl.array_size = 1; >> res_tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET |

Re: [Mesa-dev] [RFC] precursor patches to trying to merge radv

2016-09-04 Thread Nicolai Hähnle
On 05.09.2016 03:03, Dave Airlie wrote: So currently out-of-tree radv, reuses addrlib (by copying the all the files), and at least wants to share the register and family header files. This is a set of patches to just move those into a shared directory, in advance of proposing that radv goes into

[Mesa-dev] [PATCH] i965: release GLSL IR in LinkShader after it's not needed

2016-09-04 Thread Tapani Pälli
Signed-off-by: Tapani Pälli --- src/mesa/drivers/dri/i965/brw_link.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index 4800be0..2b1fa61 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b

Re: [Mesa-dev] [PATCH] intel/blorp: Work in terms of logical array layers

2016-09-04 Thread Pohjolainen, Topi
On Sat, Sep 03, 2016 at 04:09:26PM -0700, Jason Ekstrand wrote: > When Ivy Bridge introduced array multisampling, someone made the decision > to do lots of stuff throughout the driver in terms of physical array layers > rather than logical array layers. In ISL, we use logical array layers most > o

Re: [Mesa-dev] [PATCH] nir: fix definition of pack_uvec2_to_uint

2016-09-04 Thread Jason Ekstrand
Reviewed-by: Jason Ekstrand But definitely not tested-by :-) On Sun, Sep 4, 2016 at 7:47 PM, Ilia Mirkin wrote: > Found by inspection. Untested beyond compilation. > > Signed-off-by: Ilia Mirkin > --- > src/compiler/nir/nir_opcodes.py | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >

[Mesa-dev] [Bug 97587] make check nir/tests/control_flow_tests regression

2016-09-04 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=97587 Jason Ekstrand changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Mesa-dev] [PATCH] nir: fix definition of pack_uvec2_to_uint

2016-09-04 Thread Ilia Mirkin
Found by inspection. Untested beyond compilation. Signed-off-by: Ilia Mirkin --- src/compiler/nir/nir_opcodes.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index 15066c2..7045c95 100644 --- a/src/compiler/

[Mesa-dev] [PATCH 4/4] amd/addrlib: move addrlib from amdgpu winsys to common code

2016-09-04 Thread Dave Airlie
From: Dave Airlie --- src/amd/Makefile.addrlib.am| 35 ++ src/amd/Makefile.am| 3 ++ src/amd/Makefile.sources | 24 ++- .../amdgpu/drm => amd}/addrlib/addrinterface.cpp | 0 .../

[Mesa-dev] [RFC] precursor patches to trying to merge radv

2016-09-04 Thread Dave Airlie
So currently out-of-tree radv, reuses addrlib (by copying the all the files), and at least wants to share the register and family header files. This is a set of patches to just move those into a shared directory, in advance of proposing that radv goes into mainline at all. Dave.

[Mesa-dev] [PATCH 1/4] radeonsi: move sid.h/r600d_common.h to a common place.

2016-09-04 Thread Dave Airlie
From: Dave Airlie Step one to merging radv would be to move some files around. This only adds the include path to r600/radeonsi, because later we want to avoid having to add it to the generic target paths. --- configure.ac | 1 + src/Makefile.am

[Mesa-dev] [PATCH 2/4] radeon: move radeon_family/chip_class defintions to common

2016-09-04 Thread Dave Airlie
From: Dave Airlie This just moves these to a common header file. --- src/amd/Makefile.sources | 3 +- src/amd/common/amd_family.h| 111 + src/gallium/drivers/radeon/radeon_winsys.h | 86 +- 3 files changed, 115

[Mesa-dev] [PATCH 3/4] gallium/util: move endian detect into a separate file

2016-09-04 Thread Dave Airlie
From: Dave Airlie This just ports the simpler endian detection bits, addrlib sharing wants this outside gallium. --- src/gallium/include/pipe/p_config.h | 40 ++- src/util/Makefile.sources | 3 +- src/util/u_endian.h | 65 +++

[Mesa-dev] [PATCH] freedreno: pack texture buffer objects in 2d logical space

2016-09-04 Thread Ilia Mirkin
This artificially converts a buffer into a 8K x N 2D texture to fetch texels from. As a result we can access up to 8K x 8K texels on a3xx, and 16K x 16K on a4xx. This could be further expanded into 3D space if necessary, but 64M should be enough. We have to check out-of-bounds conditions in the sh

Re: [Mesa-dev] [PATCH] nir/tests: Update the CF tests to not assume fake edges

2016-09-04 Thread Connor Abbott
Reviewed-by: Connor Abbott On Sat, Sep 3, 2016 at 2:59 PM, Jason Ekstrand wrote: > In aad4f1550, we removed the concept of "fake" edges from NIR. Now, if you > have a block at the end of an infinite loop it really has no predecessors. > This updates the unit tests to match. > > Signed-off-by: J

Re: [Mesa-dev] Mesa 12.0.2 release candidate

2016-09-04 Thread Ilia Mirkin
On Thu, Sep 1, 2016 at 10:25 AM, Emil Velikov wrote: > Samuel Pitoiset (7): > nv50/ir: always emit the NDV bit for OP_QUADOP Either remove this commit, or, preferably, also cherry-pick this one: commit 61e978524a0e5de4f8570b44bcb9b907a9187684 Author: Ilia Mirkin Date: Sun Sep 4 18:21:29

Re: [Mesa-dev] [PATCH 09/10] st/vdpau: implement the new DMA-buf based interop

2016-09-04 Thread Ilia Mirkin
On Tue, Mar 8, 2016 at 7:21 AM, Christian König wrote: > @@ -80,7 +82,7 @@ vlVdpOutputSurfaceCreate(VdpDevice device, > res_tmpl.depth0 = 1; > res_tmpl.array_size = 1; > res_tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET | > - PIPE_BIND_LINEAR; > +