On Friday, September 2, 2016 7:28:09 PM PDT Connor Abbott wrote:
> In 144cbf8 ("nir: Make nir_opt_remove_phis see through moves."), Ken
> made nir_opt_remove_phis able to coalesce phi nodes whose sources are
> all moves with the same swizzle. However, he didn't add the logic
> necessary for handlin
On Friday, September 2, 2016 7:28:08 PM PDT Connor Abbott wrote:
> And re-implement nir_after_cf_node_and_phis() using it.
> ---
> src/compiler/nir/nir.h | 19 ++-
> 1 file changed, 14 insertions(+), 5 deletions(-)
Series is:
Reviewed-by: Kenneth Graunke
Thanks for fixing this!
On sáb, 2016-09-03 at 01:20 +0200, Antía Puentes wrote:
> On vie, 2016-09-02 at 17:49 -0400, Ilia Mirkin wrote:
> >
> > On Fri, Sep 2, 2016 at 5:40 PM, Antia Puentes
> > wrote:
> > >
> > >
> > > - Fixes CTS tests:
> > >
> > > * GL44-CTS.shader_image_size.advanced-nonMS-cs-float
> > > * GL44-CT
- Fixes CTS tests:
* GL44-CTS.shader_image_size.advanced-nonMS-cs-float
* GL44-CTS.shader_image_size.advanced-nonMS-cs-int
* GL44-CTS.shader_image_size.advanced-nonMS-cs-uint
* GL44-CTS.shader_image_size.advanced-nonMS-gs-float
* GL44-CTS.shader_image_size.advanced-nonMS-gs-int
* GL44-CTS.shader_i
On Fri, Sep 2, 2016 at 8:48 PM, Jason Ekstrand wrote:
> I think this is conceptually correct but I haven't reviewed it for complete
> correctness yet or tested it.
>
> That said, I think this is just a special case of the phi distribution pass
> that we talked about on IRC a bit today. Maybe we s
I think this is conceptually correct but I haven't reviewed it for complete
correctness yet or tested it.
That said, I think this is just a special case of the phi distribution pass
that we talked about on IRC a bit today. Maybe we should just go ahead and
implement that? For unary ALU operation
On Wed, Aug 31, 2016 at 8:29 PM, Nanley Chery wrote:
> This series enables Hierarchical depth buffer rendering and fast depth
> clears
> for render passes with a single subpass running on platforms BDW+.
> Platforms
> pre-BDW can test this feature with an environment variable. The FPS of some
> d
August 30 2016 8:53 AM, "Emil Velikov" wrote:
> On 25 August 2016 at 16:58, Emil Velikov wrote:
>
>> From: Emil Velikov
>>
>> The symbol is a no-op since, the EXTRA_DEBUG macro is not set in the
>> build. Unused by !Haiku people/platforms since 2010 (commit
>> a73c6540d9a7f6e26d8568ba2fc522cb
On Wed, Aug 31, 2016 at 8:29 PM, Nanley Chery wrote:
> Provides an FPS increase of ~30% on the Sascha triangle and multisampling
> demos.
>
> Clears that happen within a render pass via vkCmdClearAttachments are safe
> even if the clear color changes. This is because the meta implementation
> doe
On Fri, Sep 2, 2016 at 3:16 PM, Chad Versace
wrote:
> On Wed 31 Aug 2016, Nanley Chery wrote:
> > From: Chad Versace
> >
> > Nanley Chery:
> > (rebase)
> > - Resolve conflicts with new anv_batch_emit macro
> > (amend)
> > - Remove wip! tag and handle a QPitch TODO
> > - Emit 3DSTATE_HIER_DEPT
On Wed, Aug 31, 2016 at 8:29 PM, Nanley Chery wrote:
> From: Jason Ekstrand
>
First off, this is your patch not mine. The patch of mine you based this
on was little more than a skeleton that demonstrated how to use
PIPE_CONTROL. All of the interesting stuff in here is yours.
> Nanley Chery:
And re-implement nir_after_cf_node_and_phis() using it.
---
src/compiler/nir/nir.h | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index d0dfb0d..6852551 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/
In 144cbf8 ("nir: Make nir_opt_remove_phis see through moves."), Ken
made nir_opt_remove_phis able to coalesce phi nodes whose sources are
all moves with the same swizzle. However, he didn't add the logic
necessary for handling the fact that the phi may now have multiple
different sources, even tho
On vie, 2016-09-02 at 17:49 -0400, Ilia Mirkin wrote:
> On Fri, Sep 2, 2016 at 5:40 PM, Antia Puentes
> wrote:
> >
> > - Fixes CTS tests:
> >
> > * GL44-CTS.shader_image_size.advanced-nonMS-cs-float
> > * GL44-CTS.shader_image_size.advanced-nonMS-cs-int
> > * GL44-CTS.shader_image_size.advanced-
We already do those checks in filter_tiling. There's no good reason to
repeat them in choose_msaa_layout. If anything they should have been
asserts and not "return false" checks. Also, this check was causing us to
outright reject multisampled HiZ surfaces which wasn't intended.
---
src/intel/is
First, compressed 1D textures should be allowed. There's nothing in the
Vulkan spec (or in GL as far as I can remember) that dissallows them. It
just waists a bit of vertical space because it's only one pixel tall.
Second, the assertion that a format is uncompressed in the multisample
layouts is
---
src/intel/isl/isl.c | 60 +++--
1 file changed, 58 insertions(+), 2 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 33e83b1..cb9eb23 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1284,6 +1284,63 @@ isl_
The HiZ and CCS tiling formats are always used for HiZ and CCS surfaces
respectively. There's no reason why we should go through filter_tiling and
it's much easier to always get HiZ and CCS right if we just handle them
directly.
---
src/intel/isl/isl.c | 18 --
src/intel/isl/
This series does a few cleanups to ISL so that it can actually handle
multisampled HiZ correctly. When Chad and I first discussed HiZ, we
thought it would all work out easy as ISL already had all the required
code. We were correct that it had all the required code but wrong about
the easy part.
---
src/intel/isl/isl.h| 2 ++
src/intel/isl/isl_format.c | 30 ++
src/intel/isl/isl_gen6.c | 19 +--
src/intel/isl/isl_gen7.c | 16 +---
src/intel/isl/isl_gen8.c | 4 +---
5 files changed, 35 insertions(+), 36 deletions(-)
d
HiZ buffers can be multisampled and, on BDW+, simply using interleaved
multisampling with a compression block size of 8x4 samples yields the
correct HiZ surface size calculations. Unfortunately, choose_msaa_layout
was rejecting multisampled HiZ buffers because of format checks. Now that
we have a
I think we can just fix this by emitting another move with the right
swizzle. Then DCE should clean up the original moves, so it should
still be a win. Let me send a patch.
On Fri, Sep 2, 2016 at 4:50 PM, Kenneth Graunke wrote:
> This reverts commit 144cbf89879103c45f79b7c5b923ebad63f08c55.
>
> I
On Fri 02 Sep 2016, Nanley Chery wrote:
> On Wed, Aug 31, 2016 at 08:29:55PM -0700, Nanley Chery wrote:
> > From: Jason Ekstrand
> >
> > Nanley Chery:
> > (rebase)
> > - Resolve conflicts with the new anv_batch_emit macro
> > (amend)
> > - Update commit title
> > - Combine all HZ operations in
On Wed 31 Aug 2016, Nanley Chery wrote:
> From: Chad Versace
>
> Nanley Chery:
> (rebase)
> - Resolve conflicts with new anv_batch_emit macro
> (amend)
> - Remove wip! tag and handle a QPitch TODO
> - Emit 3DSTATE_HIER_DEPTH_BUFFER on pre-BDW systems
> - Only use HiZ for single-subpass render
On Wed, Aug 31, 2016 at 08:29:55PM -0700, Nanley Chery wrote:
> From: Jason Ekstrand
>
> Nanley Chery:
> (rebase)
> - Resolve conflicts with the new anv_batch_emit macro
> (amend)
> - Update commit title
> - Combine all HZ operations into one function
> - Add code for performing HiZ resolve o
On Fri, Sep 2, 2016 at 5:40 PM, Antia Puentes wrote:
> - Fixes CTS tests:
>
> * GL44-CTS.shader_image_size.advanced-nonMS-cs-float
> * GL44-CTS.shader_image_size.advanced-nonMS-cs-int
> * GL44-CTS.shader_image_size.advanced-nonMS-cs-uint
> * GL44-CTS.shader_image_size.advanced-nonMS-gs-float
> * G
On Wed, Aug 31, 2016 at 2:22 PM, Jason Ekstrand wrote:
> ---
> src/intel/vulkan/Makefile.sources | 1 -
> src/intel/vulkan/anv_blorp.c| 121 +
> src/intel/vulkan/anv_meta.c | 7 -
> src/intel/vulkan/anv_meta.h | 3 -
> src/intel/vulkan/anv_meta_resolve.c | 870
- Fixes CTS tests:
* GL44-CTS.shader_image_size.advanced-nonMS-cs-float
* GL44-CTS.shader_image_size.advanced-nonMS-cs-int
* GL44-CTS.shader_image_size.advanced-nonMS-cs-uint
* GL44-CTS.shader_image_size.advanced-nonMS-gs-float
* GL44-CTS.shader_image_size.advanced-nonMS-gs-int
* GL44-CTS.shader_i
On Fri, Sep 2, 2016 at 10:37 AM, Ian Romanick wrote:
> On 09/01/2016 11:15 AM, Ilia Mirkin wrote:
>> On Thu, Sep 1, 2016 at 2:10 PM, Ian Romanick wrote:
>>> + case ir_intrinsic_atomic_counter_comp_swap: {
>>> opcode = TGSI_OPCODE_ATOMCAS;
>>> param = param->get_next();
>>
On Friday, August 26, 2016 10:49:18 PM PDT Kenneth Graunke wrote:
> This fixes a numerical precision issue that was causing two CTS
> failures:
>
> ES31-CTS.blend_equation_advanced.blend_specific.GL_COLORBURN_KHR
> ES31-CTS.blend_equation_advanced.blend_all.GL_COLORBURN_KHR_all_qualifier
>
> When
This reverts commit 144cbf89879103c45f79b7c5b923ebad63f08c55.
It doesn't work. Given a phi after if/else blocks where both phi
sources are identical MOVs, it rewrites the phi destination to use
the first def it encounters...namely the result of the mov in the
then block. This results in the else
The dynamic dispatch table needs to be sorted properly, the entrypoints
shouldn't duplicate the 'glX' prefix, and please just use bsearch()
instead of open-coding it.
Signed-off-by: Adam Jackson
---
src/glx/g_glxglvnddispatchfuncs.c | 254 ++--
src/glx/g_glxglvn
On Thu, 2016-09-01 at 10:36 +0100, Emil Velikov wrote:
> > From: Emil Velikov
>
> Currently, due to the inverse order, strcmp will produce negative result
> when the needle is towards the start of the haystack. Thus on the next
> iteration(s) we'll end up further towards the end and eventually fa
On Thu 01 Sep 2016, Jason Ekstrand wrote:
>
>
> On Wed, Aug 31, 2016 at 8:29 PM, Nanley Chery wrote:
>
> From: Jason Ekstrand
>
> Nanley Chery (amend):
> - Change memset value from 0xff to 0 (a defined value for HiZ).
Yep. 0xff may hang the GPU, but 0x0 is safe.
>
> Signed
Support multi-planar YUV for external EGLImage's (currently just in the
dma-buf import path) by lowering to multiple texture fetch's for each
plane and CSC in shader.
Currently lots of TODO's, only NV12 implemented so far, only wired up in
frag shader, etc, etc..
---
src/gallium/auxiliary/util/u_
So, android and blob GLES drivers were left unchecked for too long, and
now we are stuck with this annoying OES_EGL_image_external extension and
the expectation that the driver can import multi-planar YUV buffers (via,
for example, EGL_EXT_image_dma_buf_import), despite the fact that nearly
all har
---
src/mesa/Makefile.sources | 2 +
src/mesa/state_tracker/st_tgsi_lower_yuv.c | 441 +
src/mesa/state_tracker/st_tgsi_lower_yuv.h | 34 +++
3 files changed, 477 insertions(+)
create mode 100644 src/mesa/state_tracker/st_tgsi_lower_yuv.c
create mo
On Wed, Aug 31, 2016 at 2:22 PM, Jason Ekstrand wrote:
> ---
> src/intel/vulkan/Makefile.sources | 1 -
> src/intel/vulkan/anv_blorp.c | 184
> ++
> src/intel/vulkan/anv_meta_copy.c | 180 -
> 3 files changed, 184 in
Matteo pointed out on IRC that we fail to report some format query
stuff for GL_TEXTURE_CUBE_MAP because we check for
_mesa_has_ARB_texture_cube_map(). However that ext isn't available in
core (per our extension_table.h definitions), so the helper returns
false. Looking at all of the instances of s
On Wed 31 Aug 2016, Nanley Chery wrote:
> From: Jason Ekstrand
>
> Signed-off-by: Nanley Chery
> ---
> src/intel/vulkan/anv_device.c | 20
> src/intel/vulkan/anv_image.c | 20
> 2 files changed, 20 insertions(+), 20 deletions(-)
Reviewed-by: Chad Vers
On Wed 31 Aug 2016, Nanley Chery wrote:
> From: Chad Versace
>
> Nanley Chery:
> (rebase)
> - Use isl_surf_get_hiz_surf()
> (amend)
> - Only add a HiZ surface onto a depth/stencil attachment
> - Add comment above HiZ surface addition
> - Hide HiZ behind INTEL_VK_HIZ prior to BDW
> - Remove D
On Thu, Sep 1, 2016 at 10:31 AM, Ilia Mirkin wrote:
> On Thu, Sep 1, 2016 at 10:25 AM, Emil Velikov
> wrote:
>> Ilia Mirkin (1):
>> a4xx: make sure to actually clamp depth as requested
>>
>> Ilia, for the above we require the 700+loc 9f219c7047b ("freedreno: add
>> batch-cache and batch re
On Thu 01 Sep 2016, Jason Ekstrand wrote:
> On Wed, Aug 31, 2016 at 8:29 PM, Nanley Chery wrote:
>
> From: Chad Versace
>
> Nanley Chery (amend):
> - Remove wip! tag
>
> Signed-off-by: Nanley Chery
> ---
> src/intel/vulkan/anv_private.h | 10 ++
> 1 file
On Wed 31 Aug 2016, Nanley Chery wrote:
> From: Chad Versace
>
> Unused.
>
> Nanley Chery (amend):
> - Remove wip! tag
There's no need to document that minor change :)
>
> Signed-off-by: Nanley Chery
> ---
> src/intel/vulkan/anv_private.h | 2 ++
> 1 file changed, 2 insertions(+)
_
On Wed 31 Aug 2016, Nanley Chery wrote:
> Modify extents and dimensions to match the PRMs more closely. Along with
> being able to create the correct 3D surface this enables us to avoid working
> with multisampled compressed textures.
>
> Signed-off-by: Nanley Chery
> ---
> src/intel/isl/isl.c |
On Wed 31 Aug 2016, Nanley Chery wrote:
> HiZ is not a color surface, but an auxiliary depth surface.
>
> Signed-off-by: Nanley Chery
> ---
> src/intel/isl/isl.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Chad Versace
___
me
On Fri, Sep 2, 2016 at 10:39 AM, Kenneth Graunke
wrote:
> On Thursday, September 1, 2016 7:00:01 PM PDT Connor Abbott wrote:
> > On Thu, Sep 1, 2016 at 6:19 PM, Jason Ekstrand
> wrote:
> > > On Thu, Sep 1, 2016 at 12:41 PM, Connor Abbott
> wrote:
> > >>
> > >> As-is, this change will make us de
When creating interlaced video buffer, hegith set to "template.height =
align(tmpl->height/ array_size, VL_MACROBLOCK_HEIGHT);", and we use
"template.height *= array_size;" for the buffer height, so it actually
aligned with 32. With progressive video buffer it still aligned with 16,
thus causing di
On Thursday, September 1, 2016 7:00:01 PM PDT Connor Abbott wrote:
> On Thu, Sep 1, 2016 at 6:19 PM, Jason Ekstrand wrote:
> > On Thu, Sep 1, 2016 at 12:41 PM, Connor Abbott wrote:
> >>
> >> As-is, this change will make us delete trivially infinite loops (i.e.
> >> loops with no break statement).
On Sep 2, 2016 8:55 AM, "Pohjolainen, Topi"
wrote:
>
> On Fri, Sep 02, 2016 at 07:59:15AM -0700, Jason Ekstrand wrote:
> >On Sep 2, 2016 3:07 AM, "Pohjolainen, Topi"
> ><[1]topi.pohjolai...@gmail.com> wrote:
> >>
> >> On Fri, Sep 02, 2016 at 08:34:27AM +0300, Pohjolainen, Topi wrot
On Fri, Sep 02, 2016 at 07:59:15AM -0700, Jason Ekstrand wrote:
>On Sep 2, 2016 3:07 AM, "Pohjolainen, Topi"
><[1]topi.pohjolai...@gmail.com> wrote:
>>
>> On Fri, Sep 02, 2016 at 08:34:27AM +0300, Pohjolainen, Topi wrote:
>> > On Thu, Sep 01, 2016 at 02:33:48PM -0700, Jason Ekst
On 09/02/2016 10:48 AM, Christian König wrote:
Am 02.09.2016 um 16:10 schrieb Leo Liu:
On 09/02/2016 09:50 AM, Christian König wrote:
Am 02.09.2016 um 15:27 schrieb Leo Liu:
On 09/02/2016 02:11 AM, Christian König wrote:
Am 02.09.2016 um 04:03 schrieb Michel Dänzer:
On 02/09/16 10:17 A
Am 02.09.2016 um 16:10 schrieb Leo Liu:
On 09/02/2016 09:50 AM, Christian König wrote:
Am 02.09.2016 um 15:27 schrieb Leo Liu:
On 09/02/2016 02:11 AM, Christian König wrote:
Am 02.09.2016 um 04:03 schrieb Michel Dänzer:
On 02/09/16 10:17 AM, Michel Dänzer wrote:
On 02/09/16 12:58 AM, Leo
On Sep 2, 2016 3:07 AM, "Pohjolainen, Topi"
wrote:
>
> On Fri, Sep 02, 2016 at 08:34:27AM +0300, Pohjolainen, Topi wrote:
> > On Thu, Sep 01, 2016 at 02:33:48PM -0700, Jason Ekstrand wrote:
> > >On Wed, Aug 31, 2016 at 8:17 AM, Topi Pohjolainen
> > ><[1]topi.pohjolai...@intel.com> wrote:
>
Le 02/09/2016 à 16:41, Axel Davy a écrit :
Le 02/09/2016 à 03:06, Michel Dänzer a écrit :
On 02/09/16 12:37 AM, Alex Deucher wrote:
On Thu, Sep 1, 2016 at 11:28 AM, Jason Ekstrand
wrote:
On Aug 31, 2016 11:39 PM, "Michel Dänzer" wrote:
On 01/09/16 02:05 PM, Jason Ekstrand wrote:
On Wed, Au
Le 02/09/2016 à 03:06, Michel Dänzer a écrit :
On 02/09/16 12:37 AM, Alex Deucher wrote:
On Thu, Sep 1, 2016 at 11:28 AM, Jason Ekstrand wrote:
On Aug 31, 2016 11:39 PM, "Michel Dänzer" wrote:
On 01/09/16 02:05 PM, Jason Ekstrand wrote:
On Wed, Aug 31, 2016 at 7:00 PM, Michel Dänzer mailto:
On 09/01/2016 11:15 AM, Ilia Mirkin wrote:
> On Thu, Sep 1, 2016 at 2:10 PM, Ian Romanick wrote:
>> + case ir_intrinsic_atomic_counter_comp_swap: {
>> opcode = TGSI_OPCODE_ATOMCAS;
>> param = param->get_next();
>> val = ((ir_instruction *)param)->as_rvalue();
>>
https://bugs.freedesktop.org/show_bug.cgi?id=38970
--- Comment #20 from Rahul ---
I tried locally:
and changed condition saying if Bad Magic or Error
if (__glxHashInsert(pdp->dri2Hash, xDrawable, pdraw) == -1)
then the test Passed.
--
You are receiving this mail because:
You are on the CC list
On 09/02/2016 09:50 AM, Christian König wrote:
Am 02.09.2016 um 15:27 schrieb Leo Liu:
On 09/02/2016 02:11 AM, Christian König wrote:
Am 02.09.2016 um 04:03 schrieb Michel Dänzer:
On 02/09/16 10:17 AM, Michel Dänzer wrote:
On 02/09/16 12:58 AM, Leo Liu wrote:
On 09/01/2016 11:54 AM, Naya
https://bugs.freedesktop.org/show_bug.cgi?id=38970
--- Comment #19 from Rahul ---
Hi All,
Do we have any update over this ?
what should be the expected behavior if we make multiple glXCreateGLXPixmap
with same parameters?
As Ian Told ,
it is failing because key is already in the hash table.
I
Am 02.09.2016 um 15:27 schrieb Leo Liu:
On 09/02/2016 02:11 AM, Christian König wrote:
Am 02.09.2016 um 04:03 schrieb Michel Dänzer:
On 02/09/16 10:17 AM, Michel Dänzer wrote:
On 02/09/16 12:58 AM, Leo Liu wrote:
On 09/01/2016 11:54 AM, Nayan Deshmukh wrote:
I saw the code in dri3_glx.c an
On 09/02/2016 02:11 AM, Christian König wrote:
Am 02.09.2016 um 04:03 schrieb Michel Dänzer:
On 02/09/16 10:17 AM, Michel Dänzer wrote:
On 02/09/16 12:58 AM, Leo Liu wrote:
On 09/01/2016 11:54 AM, Nayan Deshmukh wrote:
I saw the code in dri3_glx.c and I could somewhat relate some basic
code
https://bugs.freedesktop.org/show_bug.cgi?id=97260
--- Comment #36 from Jos van Wolput ---
Since your patch 1e3218bc... (loader/dri3: Overhaul dri3_update_num_back),
vblank_mode=0 glxgears shows a performance regression of about 30% of what I
got
before your patch was applied.
I am using Debian/
https://bugs.freedesktop.org/show_bug.cgi?id=97549
--- Comment #2 from Eero Tamminen ---
Created attachment 126171
--> https://bugs.freedesktop.org/attachment.cgi?id=126171&action=edit
Xorg log
(In reply to Michel Dänzer from comment #1)
> Please attach the corresponding Xorg log file.
Attach
On 02/09/16 06:12 PM, Emil Velikov wrote:
> On 2 September 2016 at 03:26, Michel Dänzer wrote:
>> On 01/09/16 11:25 PM, Emil Velikov wrote:
>>> Hello list,
>>>
>>> The candidate for the Mesa 12.0.2 is now available. Currently we have:
>>> - 160 queued
>>> - 9 nominated (outstanding)
>>> - and 1
On Fri, Sep 02, 2016 at 08:34:27AM +0300, Pohjolainen, Topi wrote:
> On Thu, Sep 01, 2016 at 02:33:48PM -0700, Jason Ekstrand wrote:
> >On Wed, Aug 31, 2016 at 8:17 AM, Topi Pohjolainen
> ><[1]topi.pohjolai...@intel.com> wrote:
> >
> > From: Topi Pohjolainen <[2]topi.pohjolai...@gmail
On 2 September 2016 at 05:35, Tapani Pälli wrote:
> Hi;
>
> Thanks, I was trying to work on the same issue but did not quite get it
> working .. will test this one with N build.
>
> FYI this patch contains both of these (which I believe were issues already
> before mentioned changes, just somehow
On 2 September 2016 at 03:26, Michel Dänzer wrote:
> On 01/09/16 11:25 PM, Emil Velikov wrote:
>> Hello list,
>>
>> The candidate for the Mesa 12.0.2 is now available. Currently we have:
>> - 160 queued
>> - 9 nominated (outstanding)
>> - and 1 rejected patches
>
> [...]
>
>> Mesa stable queue
On 25/08/16 21:49, Kristian Høgsberg wrote:
On Thu, Aug 25, 2016 at 11:38 AM, Chad Versace wrote:
On Thu 25 Aug 2016, Martin Peres wrote:
This mirrors the codepath taken by DRI2 in IntelSetTexBuffer2() and
fixes many applications when using DRI3:
- Totem with libva on hw-accelerated decodin
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