On Tue, May 10, 2016 at 04:16:35PM -0700, Jason Ekstrand wrote:
> This array allows the push constants to be re-arranged on upload. The
> actual arrangement will, eventually, come from the back-end compiler.
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 4
> src/mesa/drivers/dri/i965/brw
From: Chia-I Wu
When the depth buffer is already cleared, skip GEN6_HIZ_OP_DEPTH_CLEAR.
This is made possible by tracking which slices have been cleared in
"struct intel_mipmap_level". The hiz_cleared flag is unset when the
depth buffer is rendered to or when a HiZ resolve is needed.
Improves p
From: Michel Dänzer
This should make its meaning clearer.
The value it holds is the CPU page size, which can be different from
the GART page size.
Signed-off-by: Michel Dänzer
---
src/gallium/drivers/r300/r300_query.c | 4 +--
src/gallium/drivers/radeon/r600_pipe_common.c |
The HW has a restriction that only vertical stride may cross register
boundaries. Until now this was only handled on VGRFs at
rw_reg_from_fs_reg, but it is also needed for attributes.
v2:
* Remove reference to commit id on commit message (Juan Suarez)
* Simplify code that compute final exec_size
On 11/05/16 05:56, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> From: Connor Abbott
>>
>> v2 (Iago)
>> - Fixup accessibility in backend_reg
>>
>> Signed-off-by: Iago Toral Quiroga
>
> I've just noticed (while running valgrind) that this patch causes
> serious breakage in
Iago Toral writes:
> On Tue, 2016-05-03 at 16:21 -0700, Jordan Justen wrote:
>> On 2016-05-03 05:21:54, Samuel Iglesias Gonsálvez wrote:
>> > From: Iago Toral Quiroga
>> >
>> > The current code ignores the suboffet in the instruction's source
>> > and just uses the one from the constant. This i
The current MSAA resolve code has a special-case for if the MCS value is 0.
In this case we can only sample once because we know that all values are in
slice 0. This commit adds a second optimization that detecs the magic MCS
value that indicates the clear color and grabs the color from a push
con
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> UNIFORM_PULL_CONSTANT_LOAD is used to load a contiguous vec4 starting at a
> constant offset that is 16-byte aligned. If we need to access an unaligned
> offset we emit a load with an aligned offset and use the remaining constant
>
Samuel Iglesias Gonsálvez writes:
> From: Connor Abbott
>
> v2 (Iago)
> - Fixup accessibility in backend_reg
>
> Signed-off-by: Iago Toral Quiroga
I've just noticed (while running valgrind) that this patch causes
serious breakage in the back-end. The reason is that the extra bits
required t
On Mon, May 2, 2016 at 5:25 PM, Jonathan Gray wrote:
> On Mon, May 02, 2016 at 11:44:35AM -0700, Jason Ekstrand wrote:
> > On Mon, May 2, 2016 at 2:27 AM, Jonathan Gray wrote:
> >
> > > On Mon, May 02, 2016 at 02:23:46AM -0700, Jason Ekstrand wrote:
> > > > On May 1, 2016 11:24 PM, "Jonathan Gra
Hi Mauro,
I think you should put your name on the
Copyright section of the Android.*.mk.
I understand these files are copied.
But it's you who created and modified these files.
So it's better to use your name instead of
Intel, LunarG, ...
2016-05-11 8:31 GMT+08:00 Rob Herring :
> On Tue, May 10, 2
On 10.05.2016 19:52, Bas Nieuwenhuizen wrote:
> Signed-off-by: Bas Nieuwenhuizen
> ---
> src/gallium/drivers/radeonsi/si_shader.c | 81
>
> 1 file changed, 81 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c
> b/src/gallium/drivers/radeon
Francisco Jerez writes:
> Samuel Iglesias Gonsálvez writes:
>
>> From: Iago Toral Quiroga
>>
>> There are a few places where we need to shuffle the result of a 32-bit load
>> into valid 64-bit data, so extract this logic into a separate helper that we
>> can reuse.
>>
>> Also, the shuffling nee
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> This does the inverse operation of SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA
> and we will use it when we need to write 64-bit data in the layout expected
> by untyped write messages.
>
> Again, this needs to operate with WE_all set
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> There are a few places where we need to shuffle the result of a 32-bit load
> into valid 64-bit data, so extract this logic into a separate helper that we
> can reuse.
>
> Also, the shuffling needs to operate with WE_all set, which
https://bugs.freedesktop.org/show_bug.cgi?id=95323
--- Comment #1 from Ian Romanick ---
At least per the GLSL 1.50 specification, this test enforces NON-conformance!
The grammar makes it quite clear that
in struct { ... } foo;
declares a shader input "foo" that is an anonymous structure.
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> We were not invalidating entries with a src that reads more than one register
> when we find writes that overwrite any register read by entry->src after
> the first. This leads to incorrect copy propagation because we re-use
> entr
I recently experimented with performing rasterizer discard in the SOL
unit instead of the clipper, and as far as I can tell, it's basically
the same performance. The clipper comes directly after SOL anyway,
and setting the clipper to REJECT_ALL should be pretty darn cheap.
Keep the perf_debug on
From: Dave Airlie
Although the glsl_types.h stores this in a bitfield,
we should hide that from everyone else. Hide the cast
in an accessor method and use the enum everywhere.
This makes things a bit nicer in gdb, and improves type
safety.
Signed-off-by: Dave Airlie
---
src/compiler/glsl/ir.h
On Tue, May 10, 2016 at 6:56 PM, Mauro Rossi wrote:
> This patch adds support for libisl static, needed to build i965.
>
> Android.genxml.gen.mk generates the necessary gen%_pack.h headers
>
> Android.gen.mk generates isl_format_layout.c
[...]
> diff --git a/src/intel/isl/Makefile.sources b/src/
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> Because the stride is in units for the type, if we copy-propagate from
> a another instruction using a larger type, then we need to make sure
> that the source in that instruction, the one we will be copy-propagating
> from, source
On Friday, May 6, 2016 10:55:36 AM PDT Juan A. Suarez Romero wrote:
> Currently, when cross validating global variables, all global variables
> seen in the shaders that are part of a program are saved in a table.
>
> When checking a variable this already exist in the table, we check both
> are ini
On Thursday, May 5, 2016 5:51:18 PM PDT Jason Ekstrand wrote:
> The i965 driver has its own pass for fusing mul+add combinations that's
> much smarter than what nir_opt_algebraic can do so we don't want to get the
> nir_opt_algebraic one just because we didn't set lower_ffma.
> ---
> src/compiler/
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> We were not considering the case where the load payload is writing to
> a destination with a reg_offset > 0.
Reviewed-by: Francisco Jerez
> ---
> src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 2 +-
> 1 file changed, 1
Francisco Jerez writes:
> Samuel Iglesias Gonsálvez writes:
>
>> From: Iago Toral Quiroga
>>
>> We were not accounting for reg_suboffset in the check for the start
>> of the region. This meant that would allow copy-propagation even if
>> the dst wrote to sub_regoffset 4 and our source read from
On Wednesday, May 4, 2016 5:41:37 PM PDT Kenneth Graunke wrote:
> On Wednesday, May 4, 2016 3:54:14 PM PDT Matt Turner wrote:
> > Ken suggested instead of a big and complicated optimization pass, to
> > just recognize the operations here. It's certainly less code and a lot
> > prettier, but it seem
This patch adds support for libisl static, needed to build i965.
Android.genxml.gen.mk generates the necessary gen%_pack.h headers
Android.gen.mk generates isl_format_layout.c
---
Android.mk | 1 +
src/intel/isl/Android.gen.mk | 47
src/intel/isl
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> We were not accounting for reg_suboffset in the check for the start
> of the region. This meant that would allow copy-propagation even if
> the dst wrote to sub_regoffset 4 and our source read from
> sub_regoffset 0, which is not c
On 05/07/2016 03:05 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> ---
> src/compiler/glsl/ast_function.cpp | 4 ++--
> src/compiler/glsl/link_uniform_initializers.cpp | 8 +++-
> 2 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/src/compiler/glsl/ast_func
On 05/07/2016 03:05 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> This macro avoids undefined downcasting of list sentinels that crashes gcc's
> ubsan.
> ---
> src/compiler/glsl/list.h| 8
> src/compiler/glsl/opt_tree_grafting.cpp | 5 +
> 2 files changed, 9 i
Hi Chad,
Thanks for the review and good suggestions. I am interested to know your
opinion regarding an issue that comes up when implementing a back-buffered
pbuffer. The problem is we'll be creating a front renderbuffer, not a back
renderbuffer if we pass in single buffered visuals.
For example
As time goes on, I become less and less a fan of the proliferation of
for_* macros... especially ones that are only used in one or two places.
On 05/07/2016 03:05 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> This macro avoids undefined behaviour that crashes gcc's ubsan.
> ---
> src/com
---
src/mesa/drivers/dri/i965/Makefile.sources |2 -
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp| 1288 +--
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 145 ---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 212
src/mesa/drivers/dri/i965/brw_defin
There's no reason to be passing a whole struct around just for a single
boolean. We can create it later when we actually need to use it as a key.
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 32 +--
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/src
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index f94dd6f..27aab20 100644
--- a/src/mesa/drivers/dri/i965/brw_bl
The original code-flow tried to map original blorp. This puts things more
where they belong and simplifies some of the logic.
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 59 ++--
1 file changed, 29 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/dri/i9
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 184 ++
1 file changed, 39 insertions(+), 145 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 94b8277..3925d28 100644
--- a/src/mesa/drivers/d
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 203 +--
1 file changed, 194 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index c0c02cf..7b01da8 100644
--- a/src/mesa/drivers/dri/
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 162 ---
1 file changed, 144 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 7b01da8..83cdac5 100644
--- a/src/mesa/drivers/dri
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 35 +---
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 7067c06..ea64b11 100644
--- a/src/mesa/drivers/dri/
Many of the more complex cases still fall back to the old shader builder.
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 425 +--
1 file changed, 401 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/b
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 18 --
src/mesa/drivers/dri/i965/brw_shader.cpp | 1 +
src/mesa/drivers/dri/i965/brw_vec4.cpp| 2 ++
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 1 +
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
This commit reworks and simplifies the way we handle persample shading in
the shader key and prog_data. The previous approach had three different
key bits that had slightly different and hard-to-decern meanings while the
new bits are far more clear. This commit changes it to two easily
understood
---
src/mesa/drivers/dri/i965/brw_blorp.c | 6 +-
src/mesa/drivers/dri/i965/brw_blorp.h | 8 +++-
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 4 ++--
src/mesa/drivers/dri/i965/gen6_blorp.c| 23 +++
This is what BLORP does. Making them match cuts down on the noise when
looking at AUB diffs.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index f9bfe03..e60
The hardware packets organize kernel pointers and GRF start by slots that
don't map directly to dispatch width. This means that all of the state
setup code has to re-arrange the data from prog_data into these slots.
This logic has been duplicated 4 times in the GL driver and one more time
in the V
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 24 +++-
1 file changed, 7 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index dd22e6d..897ce99 100644
--- a/src/mesa/drivers/dri/i965/
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 120 +--
1 file changed, 114 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 83cdac5..c4d80a7 100644
--- a/src/mesa/drivers/dri/
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 107 ++-
1 file changed, 105 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 27aab20..c0c02cf 100644
--- a/src/mesa/drivers/dri/
This is similar to nir_channel except that it lets you grab more than one
channel by providing a mask.
---
src/compiler/nir/nir_builder.h | 14 ++
src/intel/vulkan/anv_meta_blit2d.c | 4 +---
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/compiler/nir/nir_buil
There's no reason for having a macro *and* a python generator. We can
easily just do the whole thing in python. This has the advantage that we
are no longer definining ALU# macros which conflict with the ones in
brw_fs_builder.h.
---
src/compiler/nir/nir_builder.h| 30 ---
Intel hardware does a form of multisample compression that involves an
auxilary surface called the MCS. When an MCS is in use, you have to first
sample from the MCS with a special opcode and then pass the result of that
operation into the next sample instrucion. Normally, we just do this
ourselve
This better matches gen8 state setup
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 17dea99..8d2e2c3 100644
--- a/src/mesa/drivers/dri
---
src/mesa/drivers/dri/i965/brw_blorp.c | 8
src/mesa/drivers/dri/i965/brw_blorp.h | 2 ++
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +-
4 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/mesa
This array allows the push constants to be re-arranged on upload. The
actual arrangement will, eventually, come from the back-end compiler.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 4
src/mesa/drivers/dri/i965/brw_blorp.h | 6 ++
src/mesa/drivers/dri/i965/gen6_blorp.c | 12 +++
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 73
1 file changed, 41 insertions(+), 32 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 71e759d..d136ba8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index c2274ba..350c14f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/s
---
src/mesa/drivers/dri/i965/brw_blorp.c | 95 +++
src/mesa/drivers/dri/i965/brw_blorp.h | 10
2 files changed, 105 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 6c3b83a..161fb90 100644
--- a/s
---
src/compiler/nir/glsl_to_nir.cpp | 1 +
src/compiler/nir/nir.h | 5 +
src/compiler/nir/nir_gather_info.c | 8 +++-
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/glsl_to_nir.cpp b/src/compiler/nir/glsl_to_nir.cpp
index e3fa623..4e50d5c 100
Now that we have a persample_shading bit in prog_data we can reduce the
amount the state setup code needs to be looking at the GL state. In
particular, it no longer pulls anything directly out of the
gl_fragment_program and no longer depends on NEW_FRAGMENT_PROGRAM.
---
src/mesa/drivers/dri/i965/
When Paul originally wrote blorp he hand-rolled a shader builder that
builds i965 shaders directly. This has caused headaches because every time
we make a change to the back-end compiler, we have to update blorp. NIR on
the other hand tends to be more stable at this point since it has many
differ
On Tuesday, May 10, 2016 3:54:05 PM PDT Jordan Justen wrote:
> Juha-Pekka found this back in May 2015:
> <1430915727-28677-1-git-send-email-juhapekka.heikk...@gmail.com>
>
> From the discussion, obviously it would be preferable to make
> ralloc_size no longer return zeroed memory, but Juha-Pekka f
Juha-Pekka found this back in May 2015:
<1430915727-28677-1-git-send-email-juhapekka.heikk...@gmail.com>
From the discussion, obviously it would be preferable to make
ralloc_size no longer return zeroed memory, but Juha-Pekka found that
it would break Mesa.
In <56af1c57.2030...@gmail.com>, Juha-P
On Tuesday, May 10, 2016 1:54:58 PM PDT Jason Ekstrand wrote:
> Otherwise constants which aren't live get an undefined constant location.
> When we go to set up param and pull_param we end up assigning all unused
> uniforms to slot 0. This cases the Vulkan driver to segfault because it
> doesn't h
Reviewed-by: Mark Janes
Jason Ekstrand writes:
> Otherwise constants which aren't live get an undefined constant location.
> When we go to set up param and pull_param we end up assigning all unused
> uniforms to slot 0. This cases the Vulkan driver to segfault because it
> doesn't have pull_pa
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> When source modifiers are present and the types of the source and
> the entry's source are different, there are certain cases in which
> we allow copy-propagation to change the type of source by the type
> of the entry's source we
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> We should not offset into them based on the relative offset of
> our source and the destination of the instruction we are copy
> propagating from, so we don't turn this:
>
> mov(16) vgrf6:F, vgrf7+0.0<0>:F
> (...)
> load_payload(8)
Otherwise constants which aren't live get an undefined constant location.
When we go to set up param and pull_param we end up assigning all unused
uniforms to slot 0. This cases the Vulkan driver to segfault because it
doesn't have pull_param.
This fixes bugs in the Vulkan driver introduced in c3
Samuel Iglesias Gonsálvez writes:
> From: Iago Toral Quiroga
>
> Specifically, consider the size of the data type of the operand to compute
> the number of registers written.
> ---
> src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On 11 May 2016 at 04:06, Ian Romanick wrote:
> It seems like at least some of these recent fixes should be candidates
> for stable.
I didn't think they were fixing any real world problems so I hadn't
really bothered,
I think I tagged one of them so far, my goal was to try and get Haswell to pass
From: Nicolai Hähnle
The old iteration casts sentinel nodes (which are mere exec_nodes) into
whatever type we're looping over, which leads to badness (in fact, gcc's
undefined behaviour sanitizer crashes while trying to verify that we have
the correct type at hand).
These modified looping constr
On 10.05.2016 14:17, Ian Romanick wrote:
On 04/30/2016 12:24 AM, Nicolai Hähnle wrote:
From: Nicolai Hähnle
The old iteration casts sentinel nodes (which are mere exec_nodes) into
whatever type we're looping over, which leads to badness (in fact, gcc's
undefined behaviour sanitizer crashes whi
On Tuesday, May 10, 2016 6:24:39 PM PDT Juan A. Suarez Romero wrote:
> On Mon, 2016-05-09 at 23:37 -0700, Kenneth Graunke wrote:
> > void *log_data,
> > > const unsigned *assembly = NULL;
> > >
> > > unsigned nr_attributes = _mesa_bitcount_64(prog_data-
> > >inputs_read);
> > > + unsign
On Thursday, April 28, 2016 1:40:35 PM PDT Antia Puentes wrote:
> From: "Juan A. Suarez Romero"
>
> VS Thread Payload handles attributes in URB as vec4, no matter if they
> are actually single or double precision.
>
> So with double-precision types, value ends up in the registers split in
> 32bi
On Tuesday, May 3, 2016 2:21:49 PM PDT Samuel Iglesias Gonsálvez wrote:
> Hello,
>
> This series adds the final bits to support arb_gpu_shader_fp64 in the
> i965 scalar backend for BDW+ hardware. It sits on top of the previous
> series we sent last week [0] and which is going through review at the
---
doxygen/doxy.bat | 7 +++
1 file changed, 7 insertions(+)
diff --git a/doxygen/doxy.bat b/doxygen/doxy.bat
index e566ca3..408964e 100644
--- a/doxygen/doxy.bat
+++ b/doxygen/doxy.bat
@@ -6,6 +6,9 @@ doxygen swrast_setup.doxy
doxygen tnl.doxy
doxygen core.doxy
doxygen glapi.doxy
+doxyge
On Tuesday, May 3, 2016 9:26:13 PM PDT Francisco Jerez wrote:
> Instead of using the LOAD_PAYLOAD instruction (emitted through the
> emit_transpose() helper that is no longer useful and this commit
> removes) which had to be marked force_writemask_all in some cases,
> emit a series of moves to appl
Until now mcs was associated to single sampled buffers only for
fast clear purposes and it was therefore the responsibility of the
clear logic to allocate the aux buffer when needed. Now that normal
3D render or blorp blit may render with mcs enabled also, they need
to prepare the mcs just as well.
On 08.05.2016 23:29, Tobias Klausmann wrote:
On 08.05.2016 22:50, Ilia Mirkin wrote:
What exactly gets fed into the CLIPDIST and CULLDIST semantics? e.g.
is CULLDIST[0].x the first cull distance, or is it the first entity in
the combined cull/clip distance array? If the former, then this won't
On 9 May 2016 at 20:33, Rob Clark wrote:
> From: Jose Fonseca
>
> Signed-off-by: Rob Clark
> ---
> src/compiler/SConscript | 57
> +++--
> 1 file changed, 55 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/SConscript b/src/compiler/SConsc
On Tuesday, May 3, 2016 2:22:07 PM PDT Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> This does the inverse operation of SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA
> and we will use it when we need to write 64-bit data in the layout expected
> by untyped write messages.
>
> Again,
On Tuesday, May 3, 2016 2:22:04 PM PDT Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> There are a few places where we need to shuffle the result of a 32-bit load
> into valid 64-bit data, so extract this logic into a separate helper that we
> can reuse.
>
> Also, the shuffling n
On Tuesday, May 10, 2016 12:07:26 PM PDT Kenneth Graunke wrote:
> On Tuesday, May 3, 2016 2:22:00 PM PDT Samuel Iglesias Gonsálvez wrote:
> > From: Iago Toral Quiroga
> >
> > ---
> > src/mesa/drivers/dri/i965/brw_fs.cpp | 49 +
+
> --
> > 1 file changed, 47 insert
Rob Clark writes:
> From: Jose Fonseca
>
> Signed-off-by: Rob Clark
> ---
> src/compiler/SConscript | 57
> +++--
> 1 file changed, 55 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/SConscript b/src/compiler/SConscript
> index 10c79c4..
On 04/30/2016 12:24 AM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> The old iteration casts sentinel nodes (which are mere exec_nodes) into
> whatever type we're looping over, which leads to badness (in fact, gcc's
> undefined behaviour sanitizer crashes while trying to verify that we have
>
On Tuesday, May 10, 2016 2:57:03 PM PDT Rob Clark wrote:
> From: Rob Clark
>
> Some optimizations, like converting integer multiply/divide into left/
> right shifts, have additional constraints on the search expression.
> Like requiring that a variable is a constant power of two. Support
> these
On Tuesday, May 3, 2016 2:22:00 PM PDT Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 49 ++
--
> 1 file changed, 47 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
Adam Jackson writes:
> Another attempt at syncing the GLX generator scripts with xserver.
>
> Jon mentioned a couple of issues in the last series, namely that these two
> patches were still necessary:
>
> https://lists.x.org/archives/xorg-devel/2014-April/041597.html
> https://lists.x.org/archive
From: Rob Clark
Some optimizations, like converting integer multiply/divide into left/
right shifts, have additional constraints on the search expression.
Like requiring that a variable is a constant power of two. Support
these cases by allowing a fxn name to be appended to the search var
expres
https://bugs.freedesktop.org/show_bug.cgi?id=95005
--- Comment #8 from Ian Romanick ---
This seems related to a bug that was reported via the mesa-dev mailing list
back in 2013:
https://lists.freedesktop.org/archives/mesa-dev/2013-November/048843.html
--
You are receiving this mail because:
Yo
v2: Reuse the macro for bind & delete.
Note that may not be able to share the delete long-term as
pipe_compute_state contains members not in pipe_shader_state,
and we need to distinguish the pointer location if we add that
struct to the union.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/dr
It seems like at least some of these recent fixes should be candidates
for stable.
On 05/09/2016 08:37 PM, Kenneth Graunke wrote:
> On Tuesday, May 10, 2016 11:07:23 AM PDT Dave Airlie wrote:
>> From: Dave Airlie
>>
>> This fixes:
>> GL33-
> CTS.gtf33.GL3Tests.vertex_type_2_10_10_10_rev.vertex_ty
On Tue, May 10, 2016 at 08:14:00PM +0300, Pohjolainen, Topi wrote:
> On Thu, Apr 21, 2016 at 02:59:04PM +0300, Topi Pohjolainen wrote:
> > v2: Add support for blorp and removed the support for meta
> >
> > Signed-off-by: Topi Pohjolainen
> > ---
> > src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
On Mon, May 9, 2016 at 12:34 PM, Rob Clark wrote:
> From: Rob Clark
>
> Signed-off-by: Rob Clark
> ---
> src/compiler/nir/nir.h | 3 +-
> src/compiler/nir/nir_lower_io_to_temporaries.c | 56
> +-
> src/mesa/drivers/dri/i965/brw_nir.c
On Mon, May 9, 2016 at 12:33 PM, Rob Clark wrote:
> From: Rob Clark
>
> Prep work to reduce the noise in the next patch.
>
> Signed-off-by: Rob Clark
> ---
> src/compiler/nir/nir_lower_io_to_temporaries.c | 124
> ++---
> 1 file changed, 72 insertions(+), 52 deletions(-)
>
On 10.05.2016 11:36, Bas Nieuwenhuizen wrote:
On Tue, May 10, 2016 at 6:28 PM, Nicolai Hähnle wrote:
On 10.05.2016 11:25, Bas Nieuwenhuizen wrote:
On Tue, May 10, 2016 at 6:13 PM, Nicolai Hähnle
wrote:
On 10.05.2016 05:52, Bas Nieuwenhuizen wrote:
Signed-off-by: Bas Nieuwenhuizen
---
On Thu, Apr 21, 2016 at 02:59:04PM +0300, Topi Pohjolainen wrote:
> v2: Add support for blorp and removed the support for meta
>
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 3 +++
> src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 6 ++
> src/mesa
On 10.05.2016 05:53, Bas Nieuwenhuizen wrote:
Setting 028B6C_DISTRIBUTION_MODE to a non-zero value and
either setting 028B6C_NUM_DS_WAVES_PER_SIMD to a non-zero
value or storing a zero control word hang my card.
The R_028B50_VGT_TESS_DISTRIBUTION value is copied from
amdgpu-pro. Smaller values
On Mon, May 09, 2016 at 10:30:25AM -0700, Ben Widawsky wrote:
> On Mon, May 09, 2016 at 10:29:28AM -0700, Ben Widawsky wrote:
> > On Fri, May 06, 2016 at 11:38:25AM +0300, Topi Pohjolainen wrote:
> > > Until now mcs was associated to single sampled buffers only for
> > > fast clear purposes and it
Reviewed-by: Ilia Mirkin
On Tue, May 10, 2016 at 1:54 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This fixes a crash (but not the test):
> GL45-CTS.shader_texture_image_samples_tests.functional_test
>
> Signed-off-by: Dave Airlie
> ---
> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 4 ++--
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