[Mesa-dev] [Bug 62142] Mesa/demo mipmap_limits upside down with running by SOFTWARE

https://bugs.freedesktop.org/show_bug.cgi?id=62142 --- Comment #7 from meng --- Verified it. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.or

[Mesa-dev] [Bug 62142] Mesa/demo mipmap_limits upside down with running by SOFTWARE

https://bugs.freedesktop.org/show_bug.cgi?id=62142 ye.tian changed: What|Removed |Added Status|RESOLVED|VERIFIED -- You are receiving this mail becau

[Mesa-dev] [PATCH] nouveau: Add lots of comments to the buffer transfer logic

Signed-off-by: Ilia Mirkin --- This is my shot at understanding this whole transfer business. The upshot is that after reading through it and understanding it, the transfer logic does appear correct if potentially less-than-perfectly-efficient (e.g. one could keep track of ranges being read/writt

[Mesa-dev] [PATCH] nv50: Fix GPU_READING/WRITING bit removal

Signed-off-by: Ilia Mirkin --- These look like pretty obvious typos. The x |= read; x &= ~write; (or vice-versa) pattern occurs in nvc0, so I'm guessing that this is what was intended here as well. Not sure if this fixes anything in particular though. src/gallium/drivers/nouveau/nv50/nv50_state

Re: [Mesa-dev] [PATCH 3/3] gallium/radeon: use PRIu64 macro for printing uint64_t

On Sam, 2013-11-30 at 21:23 +, Emil Velikov wrote: > Signed-off-by: Emil Velikov Reviewed-by: Michel Dänzer -- Earthling Michel Dänzer| http://www.amd.com Libre software enthusiast |Mesa and X developer ___

Re: [Mesa-dev] [PATCH] i965: Don't flag gather quirks for Gen8+

On 11/29/2013 01:08 AM, Chris Forbes wrote: > My understanding is that Broadwell retains the same SCS mechanism > that Haswell has, so even if the underlying issue with this format > is not fixed, the w/a will be applied in SCS rather than needing > shader code. > > Signed-off-by: Chris Forbes >

Re: [Mesa-dev] [PATCH][9.2] st/xorg: Handle new DamageUnregister API which has only one argument

Emil Velikov schrieb: > On 29/11/13 16:23, Chí-Thanh Christopher Nguyễn wrote: >> This fixes building against the new API in X server 1.15 >> Taken from xf86-video-modesetting beca4dfb0e4d11d3729214967a1fe56ee5669831 >> from Keith Packard > Hi Chí-Thanh Christopher Nguyễn, > > Are there any Gentoo

Re: [Mesa-dev] [PATCH 0/9] DRI Image 7 support for gallium

Now includes support for Image 6 as a bonus feature, and 7 is only exposed on the gallium drivers which support dma-buf import/export. Still useful for Wayland-Prime and Mir, now also useful for DRI3000 I have tested the last versions of the patches with my radeonsi card, Keith Packard's patche

[Mesa-dev] [Bug 71944] vs-temp-array-mat3-index-col-rd test fails with SB

https://bugs.freedesktop.org/show_bug.cgi?id=71944 --- Comment #8 from Vadim Girlin --- (In reply to comment #7) > The test passes with this hack, but shouldn't instruction 116 also be in > conflict with instruction 102? Yes, it looks wrong too, probably incorrect result of that instruction is n

[Mesa-dev] [Bug 71944] vs-temp-array-mat3-index-col-rd test fails with SB

https://bugs.freedesktop.org/show_bug.cgi?id=71944 --- Comment #7 from Martin Andersson --- Thanks for the explanation. I made a hack that prevented the "y: MUL T0.y, KC0[3].x, R1.x" instruction from being added to group 13. Then those two groups became this: 0102 00fd 00200c9012

Re: [Mesa-dev] [PATCH 14/15] i965/vs: Always store pull constant offsets in GRFs on Gen8.

On 1 December 2013 00:44, Kenneth Graunke wrote: > On 11/30/2013 10:40 AM, Paul Berry wrote: > > On 12 November 2013 17:51, Kenneth Graunke > > wrote: > > > > We need to SEND from a GRF, and we can only obtain those prior to > > register allocation. > > > >

Re: [Mesa-dev] [PATCH 08/15] i965: Reserve space for "Vertex Count" in GS outputs.

On 30 November 2013 13:14, Kenneth Graunke wrote: > On 11/30/2013 10:29 AM, Paul Berry wrote: > > On 12 November 2013 17:51, Kenneth Graunke > > wrote: > > > > Signed-off-by: Kenneth Graunke > > > > --- > > src/mesa/dr

[Mesa-dev] [PATCH] Fix build when configured --with-gallium-drivers=swrast --disable-driglx-direct on platforms which don't have LIBDRM

As elsewhere, place code which relies on including xf86drm.h that has been added since the last time this was fixed under #ifdef GLX_DIRECT_RENDERING. Future work: It should be possible to build when configured --with-gallium-drivers=swrast --enable-driglx-direct without LIBDRM to build a libGL wh

Re: [Mesa-dev] [PATCH 2/3] gallium: new shader cap bit for the amount of sampler views

Reviewed-by: Brian Paul On Mon, Nov 25, 2013 at 7:43 PM, wrote: > From: Roland Scheidegger > > Ever since introducing separate sampler and sampler view max this was > really > missing. > Every driver but llvmpipe reports the same number as number of samplers for > now, so nothing should break

Re: [Mesa-dev] [PATCH 1/3] gallium/drivers: support more sampler views than samplers for more drivers

Reviewed-by: Brian Paul On Mon, Nov 25, 2013 at 7:43 PM, wrote: > From: Roland Scheidegger > > This adds support for this to more drivers, in particular for all the > "special" > ones useful for debugging. > HW drivers are left alone, some should be able to support it if they want > but > the

[Mesa-dev] [Bug 44743] Rendering artefacts with llvmpipe

https://bugs.freedesktop.org/show_bug.cgi?id=44743 Markus Koschany changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Mesa-dev] [PATCH v3] egl: add HAVE_LIBDRM define, fix EGL X11 platform

Commit a594cec broke EGL X11 backend by adding dependency between X11 and DRM backends requiring HAVE_EGL_PLATFORM_DRM defined for X11. This patch fixes the issue by adding additional define for libdrm detection independent of which backend is being compiled. Tested by compiling Mesa with '--with-

[Mesa-dev] [PATCH] nv50: report 15 max inputs for fragment programs

First off, nv50_program only has 16 in/out varyings. However reporting 16 makes 'm' become 68 in nv50_fp_linkage_validate with the varying-packing-simple piglit test. (Subverting the assert makes it compile but fail.) With this patch, varying-packing-simple passes. See: https://bugs.freedesktop.or

Re: [Mesa-dev] [PATCH 14/15] i965/vs: Always store pull constant offsets in GRFs on Gen8.

On 11/30/2013 10:40 AM, Paul Berry wrote: > On 12 November 2013 17:51, Kenneth Graunke > wrote: > > We need to SEND from a GRF, and we can only obtain those prior to > register allocation. > > This allows us to do pull constant loads without the MRF hack

[Mesa-dev] [PATCH V3 06/10] i965/Gen7: Include bitfield in the sampler key for CMS layout

We need to emit extra shader code in this case to sample the MCS surface first; we can't just blindly do this all the time since IVB will sometimes try to access the MCS surface even if disabled. V3: Use actual MSAA layout from the texture's mt, rather then computing what would have been used base