Author: clamb
Date: Thu Jul 26 02:48:21 2007
New Revision: 40518
URL: http://llvm.org/viewvc/llvm-project?rev=40518&view=rev
Log:
Add target independent MachineInstr's to represent subreg insert/extract in
MBB's. PR1350
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trun
Author: clamb
Date: Thu Jul 26 03:12:07 2007
New Revision: 40520
URL: http://llvm.org/viewvc/llvm-project?rev=40520&view=rev
Log:
Teach DAG scheduling how to properly emit subreg insert/extract machine
instructions. PR1350
Modified:
llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
llvm/trun
Author: clamb
Date: Thu Jul 26 03:18:32 2007
New Revision: 40521
URL: http://llvm.org/viewvc/llvm-project?rev=40521&view=rev
Log:
Add a MachineFunction pass, which runs post register allocation, that turns
subreg insert/extract instruction into register copies. This ensures correct
code gen if t
Author: asl
Date: Thu Jul 26 05:31:52 2007
New Revision: 40522
URL: http://llvm.org/viewvc/llvm-project?rev=40522&view=rev
Log:
Fix float initializers emission (HOST_WORDS_BIG_ENDIAN is obsolete).
We still need to verify stuff on big-endian targets and cross-compilation
on targets with different e
Author: clamb
Date: Thu Jul 26 03:01:58 2007
New Revision: 40519
URL: http://llvm.org/viewvc/llvm-project?rev=40519&view=rev
Log:
Have register info provide the inverse mapping of register->superregisters.
PR1350
Modified:
llvm/trunk/include/llvm/Target/MRegisterInfo.h
llvm/trunk/utils/T
Author: baldrick
Date: Thu Jul 26 07:52:29 2007
New Revision: 40524
URL: http://llvm.org/viewvc/llvm-project?rev=40524&view=rev
Log:
Tweak this uninitialized variable fix in a way that
minimizes the differences with mainline.
Modified:
llvm-gcc-4.2/trunk/gcc/gcc.c
Modified: llvm-gcc-4.2/trun
Author: baldrick
Date: Thu Jul 26 07:47:10 2007
New Revision: 40523
URL: http://llvm.org/viewvc/llvm-project?rev=40523&view=rev
Log:
This variable could be used uninitialized.
Modified:
llvm-gcc-4.0/trunk/gcc/gcc.c
Modified: llvm-gcc-4.0/trunk/gcc/gcc.c
URL:
http://llvm.org/viewvc/llvm-proj
Author: resistor
Date: Thu Jul 26 13:57:04 2007
New Revision: 40542
URL: http://llvm.org/viewvc/llvm-project?rev=40542&view=rev
Log:
Fix a bug introduced in my last commit.
Added:
llvm/trunk/test/Transforms/GVN/2007-07-26-NonRedundant.ll
Modified:
llvm/trunk/lib/Analysis/MemoryDependenceA
Revision: 129934
Author: echeng
Date: 2007-07-26 12:08:11 -0700 (Thu, 26 Jul 2007)
Log Message:
---
Revert. Wrong repository.
Modified Paths:
--
apple-local/branches/llvm/gcc/Makefile.in
Modified: apple-local/branches/llvm/gcc/Makefile.in
===
Author: dpatel
Date: Thu Jul 26 15:21:42 2007
New Revision: 40546
URL: http://llvm.org/viewvc/llvm-project?rev=40546&view=rev
Log:
Fix thinko. Update return status appropriately.
Modified:
llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/CondPropa
Author: evancheng
Date: Thu Jul 26 14:49:30 2007
New Revision: 40544
URL: http://llvm.org/viewvc/llvm-project?rev=40544&view=rev
Log:
Unbreak Apple style build: createDeadStoreEliminationPass must be linked in
until it's completely removed.
Modified:
llvm-gcc-4.0/trunk/gcc/llvm-linker-hack.c
Hi Dan,
I am going to revert the patch for now. Please re-commit once you
fixed it.
Thanks,
Evan
On Jul 26, 2007, at 5:05 PM, Evan Cheng wrote:
> Hi Dan,
>
> This is breaking oggenc (at least on Mac OS X / x86). Can you look
> into it?
>
> Thanks,
>
> Evan
>
> On Jul 25, 2007, at 5:31 PM, Da
Author: evancheng
Date: Thu Jul 26 20:37:47 2007
New Revision: 40547
URL: http://llvm.org/viewvc/llvm-project?rev=40547&view=rev
Log:
Reverting 40504 for now. It's breaking oggenc.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm
Hi Duncan,
Some nit picks.
1. Please don't use "Chain" for stand for function static chain. It
confuses backend guys like me. :-) "Chain" stands for control flow
dependency in the backend.
2. Purely a stylistic thing:
+SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
+
On Jul 26, 2007, at 1:12 AM, Christopher Lamb wrote:
/// EmitNode - Generate machine code for an node and needed
dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
@@ -436,6 +578,14 @@
// If machine instruction
if (Node->isTargetOpcode()) {
unsigned Opc = Node->getTarget
Hi Dan,
This is breaking oggenc (at least on Mac OS X / x86). Can you look
into it?
Thanks,
Evan
On Jul 25, 2007, at 5:31 PM, Dan Gohman wrote:
> Author: djg
> Date: Wed Jul 25 19:31:09 2007
> New Revision: 40504
>
> URL: http://llvm.org/viewvc/llvm-project?rev=40504&view=rev
> Log:
> Remove
Author: alenhar2
Date: Thu Jul 26 15:07:56 2007
New Revision: 40545
URL: http://llvm.org/viewvc/llvm-project?rev=40545&view=rev
Log:
minor improvements
Modified:
poolalloc/branches/SVA/lib/DSA/Devirt.cpp
Modified: poolalloc/branches/SVA/lib/DSA/Devirt.cpp
URL:
http://llvm.org/viewvc/llvm-pr
Author: resistor
Date: Thu Jul 26 13:26:51 2007
New Revision: 40540
URL: http://llvm.org/viewvc/llvm-project?rev=40540&view=rev
Log:
Fix a couple more bugs in the phi construction by pulling in code that does
almost the same things from LCSSA.
Added:
llvm/trunk/test/Transforms/GVN/2007-07-26-
Author: evancheng
Date: Thu Jul 26 12:45:41 2007
New Revision: 40538
URL: http://llvm.org/viewvc/llvm-project?rev=40538&view=rev
Log:
Make sure epilogue esp adjustment is placed before any terminator and pop
instructions.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Modified: llv
Author: evancheng
Date: Thu Jul 26 12:02:45 2007
New Revision: 40535
URL: http://llvm.org/viewvc/llvm-project?rev=40535&view=rev
Log:
Minor bug.
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-p
Author: djg
Date: Thu Jul 26 11:14:06 2007
New Revision: 40534
URL: http://llvm.org/viewvc/llvm-project?rev=40534&view=rev
Log:
Fix the alias analysis query in DAGCombiner to not add in two
offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.
Modified:
llvm
Author: djg
Date: Thu Jul 26 11:06:08 2007
New Revision: 40533
URL: http://llvm.org/viewvc/llvm-project?rev=40533&view=rev
Log:
Move the GET_SIDE_EFFECT_INFO logic from isInstructionTriviallyDead
to Instruction::mayWriteToMemory, fixing a FIXME, and helping
various places that call mayWriteToMemor
Author: djg
Date: Thu Jul 26 10:24:15 2007
New Revision: 40529
URL: http://llvm.org/viewvc/llvm-project?rev=40529&view=rev
Log:
In the .loc directive, print the fields as "debug" fields, so they
don't get decorated as if for immediate fields for instructions.
Modified:
llvm/trunk/lib/Target/X
Author: djg
Date: Thu Jul 26 10:11:50 2007
New Revision: 40528
URL: http://llvm.org/viewvc/llvm-project?rev=40528&view=rev
Log:
Fix a whitespace difference between CMPSSrr and CMPSDrr.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL:
Author: djg
Date: Thu Jul 26 10:11:00 2007
New Revision: 40527
URL: http://llvm.org/viewvc/llvm-project?rev=40527&view=rev
Log:
Fix a pasto in a comment.
Modified:
llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp
Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp
URL:
http://llvm.org/vi
These patches add support for taking pointers to nested
functions (a gcc extension). This is done by building
and executing a small code stub on the stack, known as
a trampoline. The LLVM part adds two new intrinsics,
llvm.init.trampoline and llvm.adjust.trampoline. The
adjust intrinsic is imple
Author: evancheng
Date: Thu Jul 26 02:35:15 2007
New Revision: 40517
URL: http://llvm.org/viewvc/llvm-project?rev=40517&view=rev
Log:
Same goes for constantpool, etc.
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL:
http://
Author: clamb
Date: Thu Jul 26 02:00:46 2007
New Revision: 40514
URL: http://llvm.org/viewvc/llvm-project?rev=40514&view=rev
Log:
Remove subreg index from MachineInstr's and also keep vregs as unsigned when
adding operands.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/tr
Should this be right after register allocation? Any reason to keep
the pseudo instructions around after allocation?
Evan
On Jul 26, 2007, at 1:18 AM, Christopher Lamb wrote:
if (addPreEmitPass(PM, Fast) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
+
+ PM.add(
Author: evancheng
Date: Thu Jul 26 14:08:44 2007
New Revision: 40543
URL: http://llvm.org/viewvc/llvm-project?rev=40543&view=rev
Log:
Restore llvm version info.
Modified:
llvm-gcc-4.0/trunk/gcc/Makefile.in
Modified: llvm-gcc-4.0/trunk/gcc/Makefile.in
URL:
http://llvm.org/viewvc/llvm-project
Author: asl
Date: Thu Jul 26 10:47:14 2007
New Revision: 40532
URL: http://llvm.org/viewvc/llvm-project?rev=40532&view=rev
Log:
This correct way to handle with globals.
This makes MultiSource/{Applications,Benchmarks} and
SingleSource/{Applications,Benchmark} (C parts) to pass
being compiled with
Author: evancheng
Date: Thu Jul 26 12:45:57 2007
New Revision: 40539
URL: http://llvm.org/viewvc/llvm-project?rev=40539&view=rev
Log:
Test case for PR1573.
Added:
llvm/trunk/test/CodeGen/X86/2007-07-25-EpilogueBug.ll
Added: llvm/trunk/test/CodeGen/X86/2007-07-25-EpilogueBug.ll
URL:
http://l
Author: djg
Date: Thu Jul 26 10:29:35 2007
New Revision: 40531
URL: http://llvm.org/viewvc/llvm-project?rev=40531&view=rev
Log:
Remove a bogus return statement, what appears to have been a pasto
from Relation::contradicts in Relation::incorporate.
Modified:
llvm/trunk/lib/Transforms/Scalar/Co
Author: djg
Date: Thu Jul 26 10:25:08 2007
New Revision: 40530
URL: http://llvm.org/viewvc/llvm-project?rev=40530&view=rev
Log:
DummyInst's member functions don't need to be virtual.
Modified:
llvm/trunk/lib/VMCore/BasicBlock.cpp
Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
URL:
http://ll
Author: clamb
Date: Thu Jul 26 02:34:40 2007
New Revision: 40516
URL: http://llvm.org/viewvc/llvm-project?rev=40516&view=rev
Log:
Add selection DAG nodes for subreg insert/extract. PR1350
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/lib/CodeGen/SelectionDAG/Leg
Author: clamb
Date: Thu Jul 26 02:03:08 2007
New Revision: 40515
URL: http://llvm.org/viewvc/llvm-project?rev=40515&view=rev
Log:
Fix 80 col violation.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
URL:
http:/
Author: evancheng
Date: Thu Jul 26 12:32:14 2007
New Revision: 40537
URL: http://llvm.org/viewvc/llvm-project?rev=40537&view=rev
Log:
Don't pollute the meaning of isUnpredicatedTerminator.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.c
Author: asl
Date: Thu Jul 26 08:18:48 2007
New Revision: 40525
URL: http://llvm.org/viewvc/llvm-project?rev=40525&view=rev
Log:
Emit globals to LLVM properly (when they appear as lvalue's)
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL
On Jul 26, 2007, at 6:30 PM, Evan Cheng wrote:
Should this be right after register allocation? Any reason to keep
the pseudo instructions around after allocation?
It should probably be after prolog/epilog insertion. As for the post
RA scheduler and branch folding, I'd think it'd be OK to p
On Jul 26, 2007, at 6:27 PM, Evan Cheng wrote:
On Jul 26, 2007, at 1:12 AM, Christopher Lamb wrote:
/// EmitNode - Generate machine code for an node and needed
dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
@@ -436,6 +578,14 @@
// If machine instruction
if (Node->isTar
There was a small mistake in the X86 error checking: i64 inreg arguments should
count as consuming two registers. Fix:
-InRegCount++;
+InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
___
llvm-commits mailing lis
Author: evancheng
Date: Thu Jul 26 12:07:03 2007
New Revision: 40536
URL: http://llvm.org/viewvc/llvm-project?rev=40536&view=rev
Log:
Fix test.
Modified:
llvm/trunk/test/CodeGen/X86/test-pic-jtbl.ll
Modified: llvm/trunk/test/CodeGen/X86/test-pic-jtbl.ll
URL:
http://llvm.org/viewvc/llvm-proj
Revision: 129933
Author: echeng
Date: 2007-07-26 11:52:21 -0700 (Thu, 26 Jul 2007)
Log Message:
---
Restore llvm version info.
Modified Paths:
--
apple-local/branches/llvm/gcc/Makefile.in
Modified: apple-local/branches/llvm/gcc/Makefile.in
==
I don't think they are target opcodes. These are similar to phi,
copyfromreg, etc. Target opcodes are those that are target specific,
I.e. not shared between targets.
Evan
Sent from my iPhone
On Jul 26, 2007, at 8:36 PM, Christopher Lamb <[EMAIL PROTECTED]
> wrote:
On Jul 26, 2007, at
Sent from my iPhone
On Jul 26, 2007, at 8:41 PM, Christopher Lamb <[EMAIL PROTECTED]
> wrote:
On Jul 26, 2007, at 6:30 PM, Evan Cheng wrote:
Should this be right after register allocation? Any reason to keep
the pseudo instructions around after allocation?
It should probably be after
On Jul 26, 2007, at 10:28 PM, Evan Cheng wrote:
I don't think they are target opcodes.
Is that a suggestion? In the implementation they are:
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Thu Jul 26
02:48:21 2007
@@ -17
On Jul 26, 2007, at 10:47 PM, Evan Cheng wrote:
Sent from my iPhone
On Jul 26, 2007, at 8:41 PM, Christopher Lamb
<[EMAIL PROTECTED]> wrote:
On Jul 26, 2007, at 6:30 PM, Evan Cheng wrote:
Should this be right after register allocation? Any reason to
keep the pseudo instructions arou
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