Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.84 -> 1.85
MachineDebugInfo.cpp updated: 1.52 -> 1.53
---
Log message:
Tighter data structure for deleted debug labels.
---
Diffs of the changes: (+20 -4)
DwarfWriter.cpp |3 +--
MachineDebugInfo.cpp | 21 +
Changes in directory llvm/include/llvm/CodeGen:
MachineDebugInfo.h updated: 1.43 -> 1.44
---
Log message:
Tighter data structure for deleted debug labels.
---
Diffs of the changes: (+2 -4)
MachineDebugInfo.h |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
Index: llvm/inclu
Changes in directory llvm/lib/CodeGen:
RegAllocLinearScan.cpp updated: 1.128 -> 1.129
---
Log message:
LinearScanner hotspot.
---
Diffs of the changes: (+2 -3)
RegAllocLinearScan.cpp |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/RegAllocLinearScan.
Changes in directory llvm/include/llvm/Target:
TargetInstrInfo.h updated: 1.96 -> 1.97
---
Log message:
fix assert comment
---
Diffs of the changes: (+1 -1)
TargetInstrInfo.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff
Changes in directory llvm/lib/CodeGen:
LLVMTargetMachine.cpp updated: 1.3 -> 1.4
---
Log message:
Don't do dead block elimination in fast mode.
---
Diffs of the changes: (+2 -1)
LLVMTargetMachine.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/LLVMT
Changes in directory llvm/lib/Target:
README.txt updated: 1.42 -> 1.43
---
Log message:
new bad case
---
Diffs of the changes: (+19 -0)
README.txt | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.42 llvm/
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.cpp updated: 1.4 -> 1.5
IA64InstrInfo.h updated: 1.2 -> 1.3
---
Log message:
implement uncond branch insertion for the branch folding pass
---
Diffs of the changes: (+11 -5)
IA64InstrInfo.cpp |7 +++
IA64InstrInfo.h |9
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.7 -> 1.8
ARMInstrInfo.h updated: 1.3 -> 1.4
ARMInstrInfo.td updated: 1.70 -> 1.71
---
Log message:
implement uncond branch insertion, mark branches with isBranch.
---
Diffs of the changes: (+13 -1)
ARMInstrInfo.cpp |
Changes in directory llvm/lib/Target/Sparc:
SparcInstrInfo.cpp updated: 1.13 -> 1.14
SparcInstrInfo.h updated: 1.9 -> 1.10
---
Log message:
implement uncond branch insertion for sparc to fix regressions from last night
due to branchfolding
---
Diffs of the changes: (+13 -0)
SparcInstrInfo.
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrInfo.cpp updated: 1.9 -> 1.10
AlphaInstrInfo.h updated: 1.5 -> 1.6
---
Log message:
implement uncond branch insertion so alpha works work branchfolding.
---
Diffs of the changes: (+11 -0)
AlphaInstrInfo.cpp |7 +++
AlphaInstrInf
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.295 -> 1.296
---
Log message:
generalize 'CaseBlock'. It really allows any comparison to be inserted.
---
Diffs of the changes: (+2 -3)
SelectionDAGISel.cpp |5 ++---
1 files changed, 2 insertions(+),
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.cpp updated: 1.5 -> 1.6
---
Log message:
fix warning about missing newline at end of file
---
Diffs of the changes: (+1 -1)
IA64InstrInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA6
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.58 -> 1.59
---
Log message:
Fix CodeGen/IA64/ret-0.ll, which has apparently been broken since some of the
isel changes happened months ago.
---
Diffs of the changes: (+6 -2)
IA64ISelDAGToDAG.cpp |8 ++--
1 f
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrInfo.cpp updated: 1.10 -> 1.11
---
Log message:
fix warning about missing newline at end of file
---
Diffs of the changes: (+1 -1)
AlphaInstrInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/Alp
On Mon, 2006-10-23 at 22:57 -0700, Chris Lattner wrote:
> n Oct 23, 2006, at 10:52 PM, Chris Lattner wrote:
> > On Oct 22, 2006, at 7:50 PM, Reid Spencer wrote:
> >
> >> Attached is a patch to implement splitting the signless DIV
> >> instruction
> >> into UDiv (unsigned), SDiv (signed), and FDiv
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGISel.h updated: 1.27 -> 1.28
---
Log message:
generalize 'CaseBlock'. It really allows any comparison to be inserted.
---
Diffs of the changes: (+7 -8)
SelectionDAGISel.h | 15 +++
1 files changed, 7 insertions(+),
Changes in directory llvm/lib/Target/Sparc:
SparcInstrInfo.cpp updated: 1.14 -> 1.15
---
Log message:
fix warning about missing newline at end of file
---
Diffs of the changes: (+1 -1)
SparcInstrInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/Spa
Chris,
Thanks for your detailed review. Obviously there's still much I need to
learn about InstCombine. I'll try to slow down a bit and review things
myself on the next patches.
Below are some comments on your comments. I've made all the changes
except for InstCombine. That will take a little m
Changes in directory llvm/test/Regression/CodeGen/IA64:
ret-0.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+5 -0)
ret-0.ll |5 +
1 files changed, 5 insertions(+)
Index: llvm/test/Regression/CodeGen/IA64/ret-0.ll
diff -c /dev/null llvm/test/Regression/C
Changes in directory llvm/include/llvm/Target:
TargetInstrInfo.h updated: 1.97 -> 1.98
---
Log message:
update comment
---
Diffs of the changes: (+3 -2)
TargetInstrInfo.h |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.8 -> 1.9
---
Log message:
fix warning about missing newline at end of file
---
Diffs of the changes: (+1 -1)
ARMInstrInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMInst
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.296 -> 1.297
---
Log message:
Generalize CaseBlock a bit more:
Rename LHSBB/RHSBB to TrueBB/FalseBB. Allow the RHS value to be null,
in which case the LHS is treated as a bool.
---
Diffs of the changes: (+7
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGISel.h updated: 1.28 -> 1.29
---
Log message:
Generalize CaseBlock a bit more:
Rename LHSBB/RHSBB to TrueBB/FalseBB. Allow the RHS value to be null,
in which case the LHS is treated as a bool.
---
Diffs of the changes: (+8 -8)
S
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.297 -> 1.298
---
Log message:
visitSwitchCase knows how to insert conditional branches well. Change
visitBr to just call visitSwitchCase, eliminating duplicate logic.
---
Diffs of the changes: (+8 -37)
Se
Changes in directory llvm/include/llvm:
LinkTimeOptimizer.h updated: 1.9 -> 1.10
---
Log message:
Instead of hard coding global prefix, use TargetAsmInfo.
Add LTO destructor.
---
Diffs of the changes: (+12 -0)
LinkTimeOptimizer.h | 12
1 files changed, 12 insertions(+)
Ind
Changes in directory llvm/tools/lto:
lto.cpp updated: 1.22 -> 1.23
---
Log message:
Instead of hard coding global prefix, use TargetAsmInfo.
Add LTO destructor.
---
Diffs of the changes: (+55 -31)
lto.cpp | 86
1 files chan
Changes in directory llvm/lib/AsmParser:
llvmAsmParser.y updated: 1.269 -> 1.270
llvmAsmParser.y.cvs updated: 1.21 -> 1.22
---
Log message:
Removed extraneous semi-colon; this was prevening the grammar file from
bison'ing correctly.
---
Diffs of the changes: (+2 -2)
llvmAsmParser.y |
Changes in directory llvm/test/Regression/CodeGen/ARM:
vargs2.ll updated: 1.1 -> 1.2
---
Log message:
expand ISD::VACOPY
---
Diffs of the changes: (+35 -17)
vargs2.ll | 52 +++-
1 files changed, 35 insertions(+), 17 deletions(-)
Index: ll
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.78 -> 1.79
---
Log message:
expand ISD::VACOPY
---
Diffs of the changes: (+1 -0)
ARMISelDAGToDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/A
Changes in directory llvm/include/llvm/CodeGen:
AsmPrinter.h updated: 1.54 -> 1.55
---
Log message:
Move getPreferredAlignmentLog from AsmPrinter to TargetData
---
Diffs of the changes: (+0 -5)
AsmPrinter.h |5 -
1 files changed, 5 deletions(-)
Index: llvm/include/llvm/CodeGen/As
Changes in directory llvm/lib/Target/Alpha:
AlphaAsmPrinter.cpp updated: 1.52 -> 1.53
---
Log message:
Move getPreferredAlignmentLog from AsmPrinter to TargetData
---
Diffs of the changes: (+1 -1)
AlphaAsmPrinter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/l
Changes in directory llvm/lib/Target/X86:
X86AsmPrinter.cpp updated: 1.204 -> 1.205
X86IntelAsmPrinter.cpp updated: 1.61 -> 1.62
---
Log message:
Move getPreferredAlignmentLog from AsmPrinter to TargetData
---
Diffs of the changes: (+2 -2)
X86AsmPrinter.cpp |2 +-
X86IntelAsmPrint
Changes in directory llvm:
Makefile.rules updated: 1.406 -> 1.407
---
Log message:
Targets should depend on all the intrinsics.td files also, otherwise they
will compute a locally wrong numbering for the intrinsics. This fixes a
nasty issue where the x86 backend started miscompiling stuff in a
Changes in directory llvm/include/llvm/Target:
TargetData.h updated: 1.40 -> 1.41
---
Log message:
Move getPreferredAlignmentLog from AsmPrinter to TargetData
---
Diffs of the changes: (+6 -0)
TargetData.h |6 ++
1 files changed, 6 insertions(+)
Index: llvm/include/llvm/Target/Ta
Changes in directory llvm/lib/Target:
TargetData.cpp updated: 1.71 -> 1.72
---
Log message:
Move getPreferredAlignmentLog from AsmPrinter to TargetData
---
Diffs of the changes: (+23 -0)
TargetData.cpp | 23 +++
1 files changed, 23 insertions(+)
Index: llvm/lib/Targ
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.201 -> 1.202
---
Log message:
Move getPreferredAlignmentLog from AsmPrinter to TargetData
---
Diffs of the changes: (+1 -1)
PPCAsmPrinter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/l
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.112 -> 1.113
---
Log message:
Move getPreferredAlignmentLog from AsmPrinter to TargetData
---
Diffs of the changes: (+0 -23)
AsmPrinter.cpp | 23 ---
1 files changed, 23 deletions(-)
Index: llvm/lib/Co
Changes in directory llvm/include/llvm/Target:
TargetData.h updated: 1.41 -> 1.42
---
Log message:
TargetData is not subclassed. So no need to have virtual method.
---
Diffs of the changes: (+1 -1)
TargetData.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include
Changes in directory llvm-poolalloc/lib/Macroscopic:
DeadFieldElimination.cpp updated: 1.3 -> 1.4
---
Log message:
Updated to newer LLVM API:
1) Changed RegisterOpt to RegisterPass
2) Changed Constant[U|S]Int to ConstantInt
---
Diffs of the changes: (+1 -1)
DeadFieldElimination.cpp |
Changes in directory llvm-poolalloc/lib/PoolAllocate:
AccessTrace.cpp updated: 1.5 -> 1.6
PointerCompress.cpp updated: 1.70 -> 1.71
PoolAllocate.cpp updated: 1.125 -> 1.126
PoolOptimize.cpp updated: 1.6 -> 1.7
TransformFunctionBody.cpp updated: 1.56 -> 1.57
---
Log message:
Updated to newer LLV
Changes in directory llvm-test/SingleSource/UnitTests/SignlessTypes:
---
Log message:
Directory /var/cvs/llvm/llvm-test/SingleSource/UnitTests/SignlessTypes added to
the repository
--> Using per-directory sticky tag `SignlessTypes'
---
Diffs of the changes: (+0 -0)
0 files changed
Changes in directory llvm-test/SingleSource/UnitTests/SignlessTypes:
Makefile added (r1.1)
div.c added (r1.1)
---
Log message:
Add a unit test directory for testing basic operations affected by the
Signless Types feature. This unit tests are aimed at making sure that
various InstCombine transfo
Changes in directory llvm-test/SingleSource/UnitTests/SignlessTypes:
Makefile updated: 1.1 -> 1.2
div.c updated: 1.1 -> 1.2
---
Log message:
Fine-grainify the tests so the output will tell us specifically which
optimization is failing.
---
Diffs of the changes: (+76 -35)
Makefile |2 -
Chris,
Here's my InstCombine feedback ..
On Mon, 2006-10-23 at 22:52 -0700, Chris Lattner wrote:
>
> Index: lib/Transforms/Scalar/InstructionCombining.cpp
> ===
> RCS
> file: /var/cvs/llvm/llvm/lib/Transforms/Scalar/InstructionComb
>
>> It would be more clear to return 0 here explicitly and mention in the
>> method comment that this returns null if no upgrading is needed.
>
> Except that's not quite the case. The function can return 0 but alter
> the OpCode argument. I'll fix the comment to explain in more detail.
Great, th
On Mon, 2006-10-23 at 22:52 -0700, Chris Lattner wrote:
> I strongly recommend adding a transformation to instcombine that will
> produce more divs with such operands. For example, changing something
> like:
>
> %X = cast uint %A to int
> %Y = sdiv int %X, 1234
> %Z = cast int %Y to uint
>
>> Also, please try to stick with the established style when modifying
>> existing code. In this case, putting the '*' in the right place,
>> capitalizing variables, etc.
>>
> Old habits die hard. I've had it drilled into my head for decades that
> putting the * next to the var name is the *wrong*
On Oct 24, 2006, at 9:45 PM, Reid Spencer wrote:
> On Mon, 2006-10-23 at 22:52 -0700, Chris Lattner wrote:
>
>> I strongly recommend adding a transformation to instcombine that will
>> produce more divs with such operands. For example, changing
>> something
>> like:
>>
>> %X = cast uint %A t
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