Changes in directory llvm/docs:
WritingAnLLVMBackend.html updated: 1.10 -> 1.11
---
Log message:
Suggest looking at the SPARC backend. How weird is that?? :)
---
Diffs of the changes: (+4 -3)
WritingAnLLVMBackend.html |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
Inde
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.96 -> 1.97
---
Log message:
Remove a completed entry.
---
Diffs of the changes: (+0 -55)
README.txt | 55 ---
1 files changed, 55 deletions(-)
Index: llvm/lib/Target/X86/
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.184 -> 1.185
---
Log message:
A little bit more build_vector enhancement for v8i16 cases.
---
Diffs of the changes: (+105 -42)
X86ISelLowering.cpp | 147 +---
1 files c
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.110 -> 1.111
---
Log message:
Some missing movlps, movhps, movlpd, and movhpd patterns.
---
Diffs of the changes: (+14 -6)
X86InstrSSE.td | 20 ++--
1 files changed, 14 insertions(+), 6 deletions(-)
Ind
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.185 -> 1.186
---
Log message:
Special case handling two wide build_vector(0, x).
---
Diffs of the changes: (+4 -4)
X86ISelLowering.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/li
Changes in directory llvm/test/Regression/CodeGen/X86:
vec_set-7.ll added (r1.1)
---
Log message:
Added a movq test case.
---
Diffs of the changes: (+10 -0)
vec_set-7.ll | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/vec_set-7.ll
diff -c /dev
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.97 -> 1.98
---
Log message:
Add a new entry.
---
Diffs of the changes: (+32 -0)
README.txt | 32
1 files changed, 32 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Targ
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.29 -> 1.30
---
Log message:
Added X86 SSE2 intrinsics which can be represented as vector_shuffles. This is
a temporary workaround for the 2-wide vector_shuffle problem (i.e. its mask
would have type v2i32 which is not legal).
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.111 -> 1.112
---
Log message:
Added X86 SSE2 intrinsics which can be represented as vector_shuffles. This is
a temporary workaround for the 2-wide vector_shuffle problem (i.e. its mask
would have type v2i32 which is not legal).
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.112 -> 1.113
---
Log message:
Explicitly specify result type for def : Pat<> patterns (if it produces a vector
result). Otherwise tblgen will pick the default (v16i8 for 128-bit vector).
---
Diffs of the changes: (+47 -45)
Changes in directory llvm/lib/Target/PowerPC:
PPCJITInfo.cpp updated: 1.18 -> 1.19
---
Log message:
No functionality changes, but cleaner code with correct comments.
---
Diffs of the changes: (+41 -35)
PPCJITInfo.cpp | 76 ++---
1 files
11 matches
Mail list logo
