Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.344 -> 1.345
---
Log message:
Scalarized vector stores need not be legal, e.g. if the vector element type
needs to be promoted or expanded. Relegalize the scalar store once created.
This fixes CodeGen/Generic/vector
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.345 -> 1.346
---
Log message:
Implement PromoteOp for VEXTRACT_VECTOR_ELT. Thsi fixes
Generic/vector.ll:test_extract_elt on non-sse X86 systems.
---
Diffs of the changes: (+54 -42)
LegalizeDAG.cpp | 96
Changes in directory llvm/test/Regression/CodeGen/Generic:
vector.ll updated: 1.7 -> 1.8
---
Log message:
Make this test harder, always check generic x86 and SSE-enabled x86.
---
Diffs of the changes: (+10 -1)
vector.ll | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.133 -> 1.134
---
Log message:
Delete dead loads in the dag. This allows us to compile
vector.ll:test_extract_elt2 into:
_test_extract_elt2:
lfd f1, 32(r3)
blr
instead of:
_test_extract_elt2:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.134 -> 1.135
---
Log message:
Remove dead *extloads. This allows us to codegen vector.ll:test_extract_elt
to:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 12, r32
;;
ldfs f8
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.346 -> 1.347
---
Log message:
Do not endian swap the operands to a store if the operands came from a vector.
This fixes UnitTests/Vector/simple.c with altivec.
---
Diffs of the changes: (+3 -3)
LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.347 -> 1.348
---
Log message:
Do not endian swap split vector loads. This fixes
UnitTests/Vector/sumarray-dbl on PPC.
Now all UnitTests/Vector/* tests pass on PPC.
---
Diffs of the changes: (+0 -2)
LegalizeDA
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.454 -> 1.455
---
Log message:
extractelement(undef,x) -> undef
---
Diffs of the changes: (+8 -6)
InstructionCombining.cpp | 14 --
1 files changed, 8 insertions(+), 6 deletions(-)
Index: ll
Changes in directory llvm/lib/VMCore:
ConstantFolding.cpp updated: 1.83 -> 1.84
---
Log message:
constant fold extractelement with undef operands.
---
Diffs of the changes: (+7 -1)
ConstantFolding.cpp |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/lib/VMCore
Changes in directory llvm/lib/Target/PowerPC:
README_ALTIVEC.txt updated: 1.8 -> 1.9
---
Log message:
add a note
---
Diffs of the changes: (+2 -0)
README_ALTIVEC.txt |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/Powe
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.62 -> 1.63
---
Log message:
Add vector_extract and vector_insert nodes.
---
Diffs of the changes: (+4 -0)
TargetSelectionDAG.td |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/TargetSelectionDAG.t
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.149 -> 1.150
X86ISelLowering.h updated: 1.48 -> 1.49
X86InstrSSE.td updated: 1.50 -> 1.51
---
Log message:
Add support to use pextrw and pinsrw to extract and insert a word element
from a 128-bit vector.
---
Diffs of the
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.122 -> 1.123
---
Log message:
Add, sub and shuffle are legal for all vector types
---
Diffs of the changes: (+9 -8)
PPCISelLowering.cpp | 17 +
1 files changed, 9 insertions(+), 8 deletions(-)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.123 -> 1.124
---
Log message:
Rearrange code a bit
---
Diffs of the changes: (+25 -21)
PPCISelLowering.cpp | 46 +-
1 files changed, 25 insertions(+), 21 deletions(-)
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.24 -> 1.25
---
Log message:
Add vperm support for all datatypes
---
Diffs of the changes: (+13 -19)
PPCInstrAltivec.td | 32 +---
1 files changed, 13 insertions(+), 19 deletions(-)
I
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.7 -> 1.8
---
Log message:
Added haddp{s|d} and hsubp{s|d} intrinsics.
---
Diffs of the changes: (+19 -0)
IntrinsicsX86.td | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/include/llvm/IntrinsicsX
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.25 -> 1.26
---
Log message:
fix a pasto
---
Diffs of the changes: (+1 -1)
PPCInstrAltivec.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llv
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.51 -> 1.52
---
Log message:
Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}.
---
Diffs of the changes: (+43 -0)
X86InstrSSE.td | 43 +++
1 files changed, 43 inserti
Changes in directory llvm/utils/TableGen:
FileLexer.l updated: 1.28 -> 1.29
FileParser.y updated: 1.41 -> 1.42
Record.cpp updated: 1.52 -> 1.53
Record.h updated: 1.56 -> 1.57
---
Log message:
Generalize the previous binary operator support and add a string concatenation
operation. This impleme
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.150 -> 1.151
X86ISelLowering.h updated: 1.49 -> 1.50
X86InstrSSE.td updated: 1.52 -> 1.53
---
Log message:
Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
INSERT_VECTOR_ELT to insert a 16-bit value i
Changes in directory llvm/test/Regression/TableGen:
strconcat.td added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+7 -0)
strconcat.td |7 +++
1 files changed, 7 insertions(+)
Index: llvm/test/Regression/TableGen/strconcat.td
diff -c /dev/null llvm/test/Regres
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.26 -> 1.27
---
Log message:
Fix 80 column violations :)
---
Diffs of the changes: (+13 -14)
PPCInstrAltivec.td | 27 +--
1 files changed, 13 insertions(+), 14 deletions(-)
Index: llvm/li
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.135 -> 1.136
---
Log message:
Delete identity shuffles, implementing
CodeGen/Generic/vector-identity-shuffle.ll
---
Diffs of the changes: (+56 -2)
DAGCombiner.cpp | 58
Changes in directory llvm/test/Regression/CodeGen/Generic:
vector-identity-shuffle.ll added (r1.1)
---
Log message:
An identity shuffle shouldn't generate any permute code.
---
Diffs of the changes: (+16 -0)
vector-identity-shuffle.ll | 16
1 files changed, 16 insertions
Changes in directory llvm-poolalloc/lib/PoolAllocate:
TransformFunctionBody.cpp updated: 1.50 -> 1.51
---
Log message:
fall back on the complete call graph to get indirect targets if needed
---
Diffs of the changes: (+9 -0)
TransformFunctionBody.cpp |9 +
1 files changed, 9 inse
Changes in directory llvm/lib/Target:
TargetData.cpp updated: 1.58 -> 1.59
---
Log message:
TargetData.cpp::getTypeInfo() was returning alignment of element type as the
alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignm
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.27 -> 1.28
---
Log message:
Pull operand asm string into base class, shrinkifying intrinsic definitions.
No functionality change.
---
Diffs of the changes: (+58 -77)
PPCInstrAltivec.td | 135 +
Changes in directory llvm/lib/Target:
README.txt updated: 1.25 -> 1.26
---
Log message:
An entry about packed type alignments.
---
Diffs of the changes: (+4 -0)
README.txt |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.28 -> 1.29
---
Log message:
Shrinkify some more intrinsic definitions.
---
Diffs of the changes: (+17 -52)
PPCInstrAltivec.td | 69 +
1 files changed, 17 insert
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.455 -> 1.456
---
Log message:
If we can look through vector operations to find the scalar version of an
extract_element'd value, do so.
---
Diffs of the changes: (+40 -0)
InstructionCombining.cpp | 40 +
Changes in directory llvm/lib/Target:
README.txt updated: 1.26 -> 1.27
---
Log message:
ADd a note
---
Diffs of the changes: (+12 -0)
README.txt | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.26 llvm/lib/Targe
Changes in directory llvm/test/Regression/Transforms/IndVarsSimplify:
2006-03-31-NegativeStride.ll added (r1.1)
---
Log message:
new testcase for PR726: http://llvm.cs.uiuc.edu/PR726
---
Diffs of the changes: (+21 -0)
2006-03-31-NegativeStride.ll | 21 +
1 files chan
Changes in directory llvm/lib/Analysis:
ScalarEvolution.cpp updated: 1.45 -> 1.46
---
Log message:
Fix Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll and
PR726: http://llvm.cs.uiuc.edu/PR726 by performing consistent signed division,
not consistent unsigned
division when evaluating sc
Changes in directory llvm/include/llvm/Analysis:
ScalarEvolutionExpander.h updated: 1.4 -> 1.5
ScalarEvolutionExpressions.h updated: 1.6 -> 1.7
---
Log message:
Fix Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll and
PR726: http://llvm.cs.uiuc.edu/PR726 by performing consistent signed
34 matches
Mail list logo
