[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.47 -> 1.48 --- Log message: Don't advance the hazard recognizer when there are no hazards and no instructions to be emitted. Don't add one to the latency of a completed instruction if the latency of the op is 0

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.td PPCHazardRecognizers.cpp PPCHazardRecognizers.h PPCISelDAGToDAG.cpp PPCInstrFormats.td PPCInstrInfo.h PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPC.td updated: 1.12 -> 1.13 PPCHazardRecognizers.cpp updated: 1.8 -> 1.9 PPCHazardRecognizers.h updated: 1.4 -> 1.5 PPCISelDAGToDAG.cpp updated: 1.163 -> 1.164 PPCInstrFormats.td updated: 1.64 -> 1.65 PPCInstrInfo.h updated: 1.12 -> 1.13 PPCInstrInf

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.td PPCInstrFormats.td PPCInstrInfo.h PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPC.td updated: 1.13 -> 1.14 PPCInstrFormats.td updated: 1.65 -> 1.66 PPCInstrInfo.h updated: 1.13 -> 1.14 PPCInstrInfo.td updated: 1.180 -> 1.181 --- Log message: Mark instructions that are cracked by the PPC970 decoder as such. --- Diffs of the

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp PPCHazardRecognizers.h

Changes in directory llvm/lib/Target/PowerPC: PPCHazardRecognizers.cpp updated: 1.9 -> 1.10 PPCHazardRecognizers.h updated: 1.5 -> 1.6 --- Log message: Handle cracked instructions in dispatch group formation. --- Diffs of the changes: (+28 -15) PPCHazardRecognizers.cpp | 41 +

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCHazardRecognizers.cpp updated: 1.10 -> 1.11 --- Log message: Fix a couple of bugs that broke the alpha tester build --- Diffs of the changes: (+2 -2) PPCHazardRecognizers.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) In

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.313 -> 1.314 --- Log message: For targets with FABS/FNEG support, lower copysign to an integer load, a select and FABS/FNEG. This speeds up a trivial (aka stupid) copysign benchmark I wrote from 6.73s to 2.64s, woo.

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.123 -> 1.124 --- Log message: add a couple of missing folds --- Diffs of the changes: (+12 -0) DAGCombiner.cpp | 12 1 files changed, 12 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCom

[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.44 -> 1.45 --- Log message: I can't convince myself that this is safe, remove the recursive call. --- Diffs of the changes: (+2 -18) TargetLowering.cpp | 20 ++-- 1 files changed, 2 insertions(+), 18 dele

[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/and_add.ll

Changes in directory llvm/test/Regression/CodeGen/PowerPC: and_add.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+11 -0) and_add.ll | 11 +++ 1 files changed, 11 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/and_add.ll diff -c /dev/null ll

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.124 -> 1.125 --- Log message: Fold X+Y -> X|Y when safe. This implements: Regression/CodeGen/PowerPC/and_add.ll a case that occurs with dynamic allocas of constant size. --- Diffs of the changes: (+19 -1) DAGC

[llvm-commits] CVS: llvm/lib/Target/README.txt

Changes in directory llvm/lib/Target: README.txt updated: 1.17 -> 1.18 --- Log message: remove two implemented items --- Diffs of the changes: (+0 -22) README.txt | 22 -- 1 files changed, 22 deletions(-) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/REA