Author: efriedma
Date: Wed Feb 13 01:56:04 2008
New Revision: 47055
URL: http://llvm.org/viewvc/llvm-project?rev=47055&view=rev
Log:
Add a note pointing to PR1996.
Modified:
llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
Modified: llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
Author: lattner
Date: Wed Feb 13 01:39:09 2008
New Revision: 47054
URL: http://llvm.org/viewvc/llvm-project?rev=47054&view=rev
Log:
In SDISel, for targets that support FORMAL_ARGUMENTS nodes, lower this
node as soon as we create it in SDISel. Previously we would lower it in
legalize. The problem
Author: lattner
Date: Wed Feb 13 01:35:30 2008
New Revision: 47053
URL: http://llvm.org/viewvc/llvm-project?rev=47053&view=rev
Log:
don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
DAGCombine is now quite good at zapifying them.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelL
Author: lattner
Date: Wed Feb 13 01:25:05 2008
New Revision: 47052
URL: http://llvm.org/viewvc/llvm-project?rev=47052&view=rev
Log:
teach dag combiner how to eliminate MERGE_VALUES nodes.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/Selection
Author: sampo
Date: Wed Feb 13 01:06:12 2008
New Revision: 47051
URL: http://llvm.org/viewvc/llvm-project?rev=47051&view=rev
Log:
readme updates
Modified:
llvm/trunk/lib/Target/PowerPC/README_ALTIVEC.txt
llvm/trunk/lib/Target/X86/README-SSE.txt
Modified: llvm/trunk/lib/Target/PowerPC/REA
Eli Friedman wrote:
> Author: efriedma
> Date: Wed Feb 13 00:55:57 2008
> New Revision: 47050
>
> URL: http://llvm.org/viewvc/llvm-project?rev=47050&view=rev
> Log:
> Add test for PR1996. (This is my first time adding a test for a
> transform, so please review.)
>
>
> Added:
> llvm/trunk/t
Author: efriedma
Date: Wed Feb 13 00:55:57 2008
New Revision: 47050
URL: http://llvm.org/viewvc/llvm-project?rev=47050&view=rev
Log:
Add test for PR1996. (This is my first time adding a test for a
transform, so please review.)
Added:
llvm/trunk/test/Transforms/GVN/2008-02-12UndefLoad.ll
A
On Feb 12, 2008, at 4:35 PM, Dan Gohman wrote:
> Convert SelectionDAG::ComputeMaskedBits to use APInt instead of
> uint64_t.
> Add an overload that supports the uint64_t interface for use by
> clients
> that haven't been updated yet.
Great! Thanks for tackling this Dan!
> +++ llvm/trunk/incl
Author: sampo
Date: Wed Feb 13 00:48:40 2008
New Revision: 47049
URL: http://llvm.org/viewvc/llvm-project?rev=47049&view=rev
Log:
Add testcase for recent legalizer change
Added:
llvm/trunk/test/CodeGen/PowerPC/vec_insert.ll
Added: llvm/trunk/test/CodeGen/PowerPC/vec_insert.ll
URL:
http://ll
Author: sampo
Date: Wed Feb 13 00:43:04 2008
New Revision: 47048
URL: http://llvm.org/viewvc/llvm-project?rev=47048&view=rev
Log:
Support legalizing insert_vector_elt on targets where the element
type is not legal.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm
On Feb 12, 2008, at 7:09 AM, Wojciech Matyjewicz wrote:
> Author: wmat
> Date: Tue Feb 12 09:09:36 2008
> New Revision: 47007
>
> URL: http://llvm.org/viewvc/llvm-project?rev=47007&view=rev
> Log:
> Fix PR2002. Suppose n is the initial value for the induction
> variable (with step 1) and m is its
On Feb 12, 2008, at 6:46 PM, Evan Cheng wrote:
> Author: evancheng
> Date: Tue Feb 12 20:46:49 2008
> New Revision: 47043
>
> URL: http://llvm.org/viewvc/llvm-project?rev=47043&view=rev
> Log:
> commuteInstr() can now commute non-ssa machine instrs.
>
> Modified:
>llvm/trunk/lib/CodeGen/Targe
On Feb 12, 2008, at 7:01 PM, Evan Cheng wrote:
> Author: evancheng
> Date: Tue Feb 12 21:01:43 2008
> New Revision: 47046
>
> URL: http://llvm.org/viewvc/llvm-project?rev=47046&view=rev
> Log:
> Initial support for copy elimination by commuting its definition MI.
Yay, thanks for tackling this Eva
On Feb 12, 2008, at 6:45 PM, Evan Cheng wrote:
> URL: http://llvm.org/viewvc/llvm-project?rev=47042&view=rev
> Log:
> Added debugging routine dumpUses.
Nice.
> +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Tue Feb 12
> 20:45:38 2008
> +#ifndef NDEBUG
> + void dumpUses(unsigned RegN
Author: evancheng
Date: Tue Feb 12 21:23:53 2008
New Revision: 47047
URL: http://llvm.org/viewvc/llvm-project?rev=47047&view=rev
Log:
New tests.
Added:
llvm/trunk/test/CodeGen/X86/coalescer-commute1.ll
llvm/trunk/test/CodeGen/X86/coalescer-commute2.ll
llvm/trunk/test/CodeGen/X86/coale
Author: evancheng
Date: Tue Feb 12 21:01:43 2008
New Revision: 47046
URL: http://llvm.org/viewvc/llvm-project?rev=47046&view=rev
Log:
Initial support for copy elimination by commuting its definition MI.
PR1877.
A3 = op A2 B0
Author: sampo
Date: Tue Feb 12 20:58:33 2008
New Revision: 47045
URL: http://llvm.org/viewvc/llvm-project?rev=47045&view=rev
Log:
Make register scavenging happy by not using a reg (CR0) that isn't defined
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
Modified: llvm/trunk/lib/Target
Author: evancheng
Date: Tue Feb 12 20:48:26 2008
New Revision: 47044
URL: http://llvm.org/viewvc/llvm-project?rev=47044&view=rev
Log:
- Added removeValNo() to remove all live ranges of a particular value#.
- removeRange() can now update value# information.
Modified:
llvm/trunk/include/llvm/Co
Author: evancheng
Date: Tue Feb 12 20:46:49 2008
New Revision: 47043
URL: http://llvm.org/viewvc/llvm-project?rev=47043&view=rev
Log:
commuteInstr() can now commute non-ssa machine instrs.
Modified:
llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.
Author: evancheng
Date: Tue Feb 12 20:45:38 2008
New Revision: 47042
URL: http://llvm.org/viewvc/llvm-project?rev=47042&view=rev
Log:
Added debugging routine dumpUses.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
Modified:
Author: djg
Date: Tue Feb 12 18:35:47 2008
New Revision: 47039
URL: http://llvm.org/viewvc/llvm-project?rev=47039&view=rev
Log:
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been update
Author: johannes
Date: Tue Feb 12 17:35:09 2008
New Revision: 47037
URL: http://llvm.org/viewvc/llvm-project?rev=47037&view=rev
Log:
__DATA not __DATA__ is the right segment name on darwin.
Spotted by Nick Kledzik.
Modified:
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Targ
Author: sampo
Date: Tue Feb 12 16:54:40 2008
New Revision: 47036
URL: http://llvm.org/viewvc/llvm-project?rev=47036&view=rev
Log:
Remove some dead code
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL:
http://llvm.org/viewvc
On Feb 12, 2008, at 12:00 AM, Evan Cheng wrote:
>
> On Feb 10, 2008, at 8:19 PM, Nate Begeman wrote:
>
>>
>> +
>> + if (Subtarget->hasSSE41()) {
>> ...
> ...
>>
>> +if (Subtarget->is64Bit()) {
>> + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64,
>> Legal);
>> + setOperatio
Author: sampo
Date: Tue Feb 12 16:51:28 2008
New Revision: 47035
URL: http://llvm.org/viewvc/llvm-project?rev=47035&view=rev
Log:
SSE4.1 64b integer insert/extract pattern support
Move formats into the formats file
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Tar
Author: djg
Date: Tue Feb 12 15:47:33 2008
New Revision: 47032
URL: http://llvm.org/viewvc/llvm-project?rev=47032&view=rev
Log:
Change APInt::getBitsSet to accept a "half-open" range, where the
hiBit parameter marks the index one past the last desired set bit.
Modified:
llvm/trunk/include/llv
On Feb 12, 2008, at 11:27 AM, Dan Gohman wrote:
> Hi Chris,
>
> Thanks for the careful review! I've responded to parts of it already,
> and I'll
> be responding to more soon.
Thanks Dan!
> On Feb 10, 2008, at 11:56 AM, Chris Lattner wrote:
>> Instead of Size here, would it make sense to store a
Author: baldrick
Date: Tue Feb 12 15:40:21 2008
New Revision: 47031
URL: http://llvm.org/viewvc/llvm-project?rev=47031&view=rev
Log:
Note that these instructions are for x86-32 linux
(the only platform on which the Ada compiler even
builds).
Modified:
llvm/trunk/docs/CFEBuildInstrs.html
Modi
On Feb 12, 2008, at 1:23 PM, Duncan Sands wrote:
> Author: baldrick
> Date: Tue Feb 12 15:22:58 2008
> New Revision: 47027
>
> URL: http://llvm.org/viewvc/llvm-project?rev=47027&view=rev
> Log:
> Add instructions for building Ada and Fortran.
> Adjust mentions of gcc4 to be 4.0/4.2 agnostic.
> Th
Author: baldrick
Date: Tue Feb 12 15:28:39 2008
New Revision: 47028
URL: http://llvm.org/viewvc/llvm-project?rev=47028&view=rev
Log:
Add more spacing.
Modified:
llvm/trunk/docs/CFEBuildInstrs.html
Modified: llvm/trunk/docs/CFEBuildInstrs.html
URL:
http://llvm.org/viewvc/llvm-project/llvm/tr
Author: baldrick
Date: Tue Feb 12 15:22:58 2008
New Revision: 47027
URL: http://llvm.org/viewvc/llvm-project?rev=47027&view=rev
Log:
Add instructions for building Ada and Fortran.
Adjust mentions of gcc4 to be 4.0/4.2 agnostic.
This file should probably be renamed tor
GCCFEBuildInstrs.html...
Mo
Author: resistor
Date: Tue Feb 12 15:15:18 2008
New Revision: 47026
URL: http://llvm.org/viewvc/llvm-project?rev=47026&view=rev
Log:
Re-apply the patch to improve the optimizations of memcpy's, with several
bugs fixed. This now passes PPC bootstrap.
Modified:
llvm/trunk/include/llvm/Analysis
Author: laurov
Date: Tue Feb 12 14:59:25 2008
New Revision: 47025
URL: http://llvm.org/viewvc/llvm-project?rev=47025&view=rev
Log:
Reduce test size.
Modified:
test-suite/trunk/SingleSource/Benchmarks/Misc/oourafft.c
Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/oourafft.c
URL:
ht
Author: baldrick
Date: Tue Feb 12 14:46:31 2008
New Revision: 47024
URL: http://llvm.org/viewvc/llvm-project?rev=47024&view=rev
Log:
Generalize getCopyFromParts and getCopyToParts to
handle arbitrary precision integers and any number
of parts. For example, on a 32 bit machine an i50
corresponds t
Author: criswell
Date: Tue Feb 12 14:33:14 2008
New Revision: 47023
URL: http://llvm.org/viewvc/llvm-project?rev=47023&view=rev
Log:
Added getPoolType() method which allows other passes to determine the type
of pool descriptors added by the Automatic Pool Allocation pass.
Modified:
poolalloc/
Author: laurov
Date: Tue Feb 12 14:16:49 2008
New Revision: 47022
URL: http://llvm.org/viewvc/llvm-project?rev=47022&view=rev
Log:
Define SMALL_PROBLEM_SIZE.
Modified:
test-suite/trunk/SingleSource/Benchmarks/Misc-C++/ray.cpp
test-suite/trunk/SingleSource/Benchmarks/Misc-C++/sphereflake.
Changes in directory llvm-www/pubs:
index.html updated: 1.63 -> 1.64
---
Log message:
add to index page
---
Diffs of the changes: (+3 -0)
index.html |3 +++
1 files changed, 3 insertions(+)
Index: llvm-www/pubs/index.html
diff -u llvm-www/pubs/index.html:1.63 llvm-www/pubs/index.html
Changes in directory llvm-www/pubs:
2008-02-23-TRANSACT-TangerObjBased.html added (r1.1)
2008-02-23-TRANSACT-TangerObjBased.pdf added (r1.1)
---
Log message:
new paper from Torvald Riegel
---
Diffs of the changes: (+49 -0)
2008-02-23-TRANSACT-TangerObjBased.html | 49
Hi Chris,
Thanks for the careful review! I've responded to parts of it already,
and I'll
be responding to more soon.
On Feb 10, 2008, at 11:56 AM, Chris Lattner wrote:
>
> Instead of Size here, would it make sense to store an MVT? That would
> seem to capture strictly more information, though
Author: evancheng
Date: Tue Feb 12 13:25:12 2008
New Revision: 47020
URL: http://llvm.org/viewvc/llvm-project?rev=47020&view=rev
Log:
Revert r46916 PPCTargetAsmInfo.cpp.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
Author: evancheng
Date: Tue Feb 12 13:20:46 2008
New Revision: 47019
URL: http://llvm.org/viewvc/llvm-project?rev=47019&view=rev
Log:
Only using x86-64 rip relative addressing in non-staic mode?
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/X86IS
Author: evancheng
Date: Tue Feb 12 13:11:29 2008
New Revision: 47018
URL: http://llvm.org/viewvc/llvm-project?rev=47018&view=rev
Log:
Don't mask the isel bug.
Modified:
llvm/trunk/test/CodeGen/X86/fold-mul-lohi.ll
llvm/trunk/test/CodeGen/X86/stride-nine-with-base-reg.ll
llvm/trunk/tes
Author: evancheng
Date: Tue Feb 12 13:11:08 2008
New Revision: 47017
URL: http://llvm.org/viewvc/llvm-project?rev=47017&view=rev
Log:
This test assumes no SSE4.1.
Modified:
llvm/trunk/test/CodeGen/X86/peep-vector-extract-concat.ll
Modified: llvm/trunk/test/CodeGen/X86/peep-vector-extract-con
Evan Cheng wrote:
> Any idea what the differences mean? .rodata.cst4 makes it possible to
> be merged? Was there a reason to change it or than to match gcc?
You're right, this is a bad patch. I changed it because I was getting
errors in the assembler with it, but then, that's not what changed t
Author: djg
Date: Tue Feb 12 12:52:52 2008
New Revision: 47015
URL: http://llvm.org/viewvc/llvm-project?rev=47015&view=rev
Log:
Add a doxygen comment for SrcValueSDNode, to make its purpose
clear and to clarify how it differs from MemOperandSDNode.
Modified:
llvm/trunk/include/llvm/CodeGen/Se
On Feb 12, 2008, at 10:38 AM, Dan Gohman wrote:
>
> On Feb 12, 2008, at 12:12 AM, Evan Cheng wrote:
+
+// Save loads/stores matched by a pattern.
+if (!N->isLeaf() && N->getName().empty()) {
+ std::string EnumName = N->getOperator()-
>getValueAsString("
On Feb 12, 2008, at 12:12 AM, Evan Cheng wrote:
>>>
>>> +
>>> +// Save loads/stores matched by a pattern.
>>> +if (!N->isLeaf() && N->getName().empty()) {
>>> + std::string EnumName = N->getOperator()-
>>> >getValueAsString("Opcode");
>>> + if (EnumName == "ISD::LOAD" ||
>>> +
Hi Eli,
Could you add a regression test from the testcase in the PR, to
verify that the load is optimized out?
Thanks,
Dan
On Feb 12, 2008, at 4:08 AM, Eli Friedman wrote:
> Author: efriedma
> Date: Tue Feb 12 06:08:14 2008
> New Revision: 47006
>
> URL: http://llvm.org/viewvc/llvm-project?rev
Author: dpatel
Date: Tue Feb 12 12:20:50 2008
New Revision: 47012
URL: http://llvm.org/viewvc/llvm-project?rev=47012&view=rev
Log:
Remove dead code.
Modified:
llvm/trunk/utils/buildit/build_llvm
Modified: llvm/trunk/utils/buildit/build_llvm
URL:
http://llvm.org/viewvc/llvm-project/llvm/trun
Author: laurov
Date: Tue Feb 12 12:16:07 2008
New Revision: 47011
URL: http://llvm.org/viewvc/llvm-project?rev=47011&view=rev
Log:
Fix test case.
Modified:
test-suite/trunk/MultiSource/Benchmarks/Prolangs-C/plot2fig/plot.c
Modified: test-suite/trunk/MultiSource/Benchmarks/Prolangs-C/plot2fi
Author: efriedma
Date: Tue Feb 12 06:08:14 2008
New Revision: 47006
URL: http://llvm.org/viewvc/llvm-project?rev=47006&view=rev
Log:
Fix for bug 1996: optimize out loads of undef. This code basically just
checks for a malloc/alloca immediately followed by a load.
Modified:
llvm/trunk/lib/Tr
On Feb 12, 2008, at 5:17 AM, Duncan Sands wrote:
> Hi Dale,
>
Treat struct { long long: 29; }; as int sized and
aligned, rather than long long. ABI issue.
>>>
>>> if you look at the DECL_SIZE of the bitfield, rather than
>>> the type size, I think it gives you 29. If so, DECL_SIZE
>>>
Author: wmat
Date: Tue Feb 12 09:12:40 2008
New Revision: 47009
URL: http://llvm.org/viewvc/llvm-project?rev=47009&view=rev
Log:
Now that ScalarEvolution::print writes to the correct stream, there is
no need to redirect stderr into stdout.
Modified:
llvm/trunk/test/Analysis/ScalarEvolution/2
Author: wmat
Date: Tue Feb 12 09:09:36 2008
New Revision: 47007
URL: http://llvm.org/viewvc/llvm-project?rev=47007&view=rev
Log:
Fix PR2002. Suppose n is the initial value for the induction
variable (with step 1) and m is its final value. Then, the correct trip
count is SMAX(m,n)-n. Previously,
Author: wmat
Date: Tue Feb 12 09:10:35 2008
New Revision: 47008
URL: http://llvm.org/viewvc/llvm-project?rev=47008&view=rev
Log:
Change negative grep into positive one in my yesterday's testcase.
Modified:
llvm/trunk/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll
Modified:
ll
Hi Dale,
> >> Treat struct { long long: 29; }; as int sized and
> >> aligned, rather than long long. ABI issue.
> >
> > if you look at the DECL_SIZE of the bitfield, rather than
> > the type size, I think it gives you 29. If so, DECL_SIZE
> > should simplify things for you. In fact as far as I
=
=
=
=
=
=
=
=
=
=
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Wed Feb 6
16:27:42 2008
@@ -313,6 +313,12 @@
std::vector > OrigChains;
std::set Duplicates
On Feb 10, 2008, at 8:19 PM, Nate Begeman wrote:
>
> +
> + if (Subtarget->hasSSE41()) {
> ...
...
>
> +if (Subtarget->is64Bit()) {
> + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
> + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Legal);
> +
> + se
Author: evancheng
Date: Tue Feb 12 01:59:55 2008
New Revision: 47002
URL: http://llvm.org/viewvc/llvm-project?rev=47002&view=rev
Log:
Update comment.
Modified:
llvm/trunk/lib/Target/X86/X86Subtarget.h
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL:
http://llvm.org/viewvc/llvm-projec
Author: evancheng
Date: Tue Feb 12 01:59:45 2008
New Revision: 47001
URL: http://llvm.org/viewvc/llvm-project?rev=47001&view=rev
Log:
Unbreak various insert_vector_elt and extract_vector_elt tests in presence of
SSE4.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/tr
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