Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.109 -> 1.110
ARMISelLowering.cpp updated: 1.24 -> 1.25
ARMInstrInfo.cpp updated: 1.16 -> 1.17
ARMInstrInfo.td updated: 1.90 -> 1.91
ARMInstrThumb.td updated: 1.16 -> 1.17
ARMRegisterInfo.cpp updated: 1.82 -> 1.83
---
Log me
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.108 -> 1.109
ARMInstrInfo.td updated: 1.89 -> 1.90
ARMInstrThumb.td updated: 1.15 -> 1.16
---
Log message:
Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for cons
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.88 -> 1.89
ARMInstrThumb.td updated: 1.14 -> 1.15
---
Log message:
Constant generation instructions are re-materializable.
---
Diffs of the changes: (+11 -5)
ARMInstrInfo.td | 15 ++-
ARMInstrThumb.td |1
Changes in directory llvm/lib/Target:
Target.td updated: 1.94 -> 1.95
---
Log message:
Added isReMaterializable.
---
Diffs of the changes: (+1 -0)
Target.td |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.94 llvm/lib/Target/Ta
Changes in directory llvm/utils/TableGen:
CodeGenInstruction.h updated: 1.25 -> 1.26
CodeGenTarget.cpp updated: 1.85 -> 1.86
InstrInfoEmitter.cpp updated: 1.56 -> 1.57
---
Log message:
Recognize target instruction flag 'isReMaterializable'.
---
Diffs of the changes: (+3 -0)
CodeGenInstructi
Changes in directory llvm/include/llvm/Target:
TargetInstrInfo.h updated: 1.113 -> 1.114
---
Log message:
Add a TargetInstrDescriptor flag to mark an instruction as "re-materializable".
It means the instruction can be easily re-materialized at any point. e.g.
constant generation, load from cons
Changes in directory llvm/lib/Target/CBackend:
Writer.cpp updated: 1.280.4.1 -> 1.280.4.2
---
Log message:
Make the given functions with the const attribute.
No, this should never be folded into a non-experimental LLVM branch.
---
Diffs of the changes: (+8 -0)
Writer.cpp |8
1
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.42 -> 1.43
---
Log message:
Add isStrictPositive() to APInt to determine if this APInt Value > 0.
---
Diffs of the changes: (+6 -0)
APInt.h |6 ++
1 files changed, 6 insertions(+)
Index: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm-test:
Makefile.programs updated: 1.261 -> 1.262
---
Log message:
Reset x86 llcbeta to -enable-tail-merge.
---
Diffs of the changes: (+1 -2)
Makefile.programs |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm-test/Makefile.programs
diff -u ll
Changes in directory llvm-test/MultiSource/Applications/minisat:
Makefile updated: 1.8 -> 1.9
---
Log message:
work around a libtool bug.
---
Diffs of the changes: (+4 -0)
Makefile |4
1 files changed, 4 insertions(+)
Index: llvm-test/MultiSource/Applications/minisat/Makefile
di
Changes in directory llvm/lib/CodeGen:
LiveIntervalAnalysis.cpp updated: 1.223 -> 1.224
---
Log message:
Minor bug fix.
---
Diffs of the changes: (+1 -1)
LiveIntervalAnalysis.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
dif
Changes in directory llvm-www:
OpenProjects.html updated: 1.21 -> 1.22
---
Log message:
Add new idea
---
Diffs of the changes: (+9 -1)
OpenProjects.html | 10 +-
1 files changed, 9 insertions(+), 1 deletion(-)
Index: llvm-www/OpenProjects.html
diff -u llvm-www/OpenProjects.html
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.372 -> 1.373
---
Log message:
fix a warning
---
Diffs of the changes: (+1 -1)
X86ISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm
Changes in directory llvm/test/Transforms/ScalarRepl:
memset-aggregate-byte-leader.ll updated: 1.1 -> 1.2
---
Log message:
add PR#
---
Diffs of the changes: (+1 -0)
memset-aggregate-byte-leader.ll |1 +
1 files changed, 1 insertion(+)
Index: llvm/test/Transforms/ScalarRepl/memset-agg
Changes in directory llvm/lib/Transforms/Scalar:
ScalarReplAggregates.cpp updated: 1.78 -> 1.79
---
Log message:
implement the next chunk of SROA with memset/memcpy's of aggregates. This
implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll
---
Diffs of the changes: (+107 -36)
Changes in directory llvm/test/Transforms/ScalarRepl:
memset-aggregate.ll updated: 1.1 -> 1.2
---
Log message:
add pr#
---
Diffs of the changes: (+1 -0)
memset-aggregate.ll |1 +
1 files changed, 1 insertion(+)
Index: llvm/test/Transforms/ScalarRepl/memset-aggregate.ll
diff -u llvm/t
Changes in directory llvm/test/Transforms/ScalarRepl:
memset-aggregate-byte-leader.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+20 -0)
memset-aggregate-byte-leader.ll | 20
1 files changed, 20 insertions(+)
Index: llvm/test/Transforms/S
Changes in directory llvm/test/Transforms/ScalarRepl:
memset-aggregate.ll added (r1.1)
---
Log message:
testcase for SROA with memset etc
---
Diffs of the changes: (+48 -0)
memset-aggregate.ll | 48
1 files changed, 48 insertions(+)
Inde
Changes in directory llvm-www/pubs:
2007-03-12-BossaLLVMIntro.pdf updated: 1.1 -> 1.2
---
Log message:
Update
---
Diffs of the changes: (+0 -0)
2007-03-12-BossaLLVMIntro.pdf |0
1 files changed
Index: llvm-www/pubs/2007-03-12-BossaLLVMIntro.pdf
___
Changes in directory llvm/lib/Transforms/Scalar:
PredicateSimplifier.cpp updated: 1.59 -> 1.60
---
Log message:
Clean up this code and fix subtract miscompile.
---
Diffs of the changes: (+22 -18)
PredicateSimplifier.cpp | 40 ++--
1 files changed, 22 i
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.661 -> 1.662
---
Log message:
Implement InstCombine/and-xor-merge.ll:test[12].
Rearrange some code to simplify it now that shifts are binops
---
Diffs of the changes: (+95 -53)
InstructionCombining.cpp |
Changes in directory llvm/test/Transforms/InstCombine:
and-xor-merge.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+19 -0)
and-xor-merge.ll | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/test/Transforms/InstCombine/and-xor-merge.ll
di
Changes in directory llvm/lib/Target:
README.txt updated: 1.57 -> 1.58
---
Log message:
minor updates
---
Diffs of the changes: (+6 -8)
README.txt | 14 ++
1 files changed, 6 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:
Changes in directory llvm/lib/Target:
README.txt updated: 1.56 -> 1.57
---
Log message:
This is implemented. We now generate:
entry:
icmp ugt i32 %x, 4 ; :0 [#uses=1]
br i1 %0, label %cond_true, label %cond_false
cond_true: ; preds = %entry
%t
Changes in directory llvm/lib/CodeGen:
PHIElimination.cpp updated: 1.54 -> 1.55
TwoAddressInstructionPass.cpp updated: 1.45 -> 1.46
---
Log message:
Keep UsedBlocks info accurate.
---
Diffs of the changes: (+6 -0)
PHIElimination.cpp|3 +++
TwoAddressInstructionPass.cpp |
Changes in directory llvm/lib/CodeGen:
LiveIntervalAnalysis.cpp updated: 1.222 -> 1.223
---
Log message:
- Merge UsedBlocks info after two virtual registers are coalesced.
- Use distance to closest use to determine whether to abort coalescing.
---
Diffs of the changes: (+30 -23)
LiveInterva
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