[llvm-commits] CVS: llvm/docs/BytecodeFormat.html

Changes in directory llvm/docs: BytecodeFormat.html updated: 1.53 -> 1.54 --- Log message: Document the VAArg, and vector instruction opcodes. --- Diffs of the changes: (+13 -3) BytecodeFormat.html | 16 +--- 1 files changed, 13 insertions(+), 3 deletions(-) Index: llvm/doc

[llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp

Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.200 -> 1.201 --- Log message: Align stack size to DWORD boundary --- Diffs of the changes: (+3 -0) X86AsmPrinter.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u ll

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/ARM: ARMISelDAGToDAG.cpp updated: 1.69 -> 1.70 --- Log message: expand ISD::BRCOND --- Diffs of the changes: (+2 -0) ARMISelDAGToDAG.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff -u llvm/lib/Target

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/fpcmp.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: fpcmp.ll updated: 1.3 -> 1.4 --- Log message: fix some fp condition codes use non trapping comparison instructions --- Diffs of the changes: (+2 -4) fpcmp.ll |6 ++ 1 files changed, 2 insertions(+), 4 deletions(-) Index: llvm

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMISelDAGToDAG.cpp updated: 1.68 -> 1.69 ARMInstrInfo.td updated: 1.48 -> 1.49 --- Log message: fix some fp condition codes use non trapping comparison instructions --- Diffs of the changes: (+28 -41) ARMISelDAGToDAG.cpp | 60 +++

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.223 -> 1.224 --- Log message: Tidy up after truncstore changes. --- Diffs of the changes: (+9 -46) DAGCombiner.cpp | 55 +-- 1 files changed, 9 insertions(+),

[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-10-13-CycleInDAG.ll

Changes in directory llvm/test/Regression/CodeGen/X86: 2006-10-13-CycleInDAG.ll added (r1.1) --- Log message: One cyclic dag a day is good for ya... --- Diffs of the changes: (+20 -0) 2006-10-13-CycleInDAG.ll | 20 1 files changed, 20 insertions(+) Index: llvm/test/

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.118 -> 1.119 --- Log message: Corrected load folding check. We need to start from the root of the sub-dag being matched and ensure there isn't a non-direct path to the load (i.e. a path that goes out of the sub-dag.) ---

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp ScheduleDAGRRList.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.103 -> 1.104 ScheduleDAGRRList.cpp updated: 1.14 -> 1.15 --- Log message: Debug tweak. --- Diffs of the changes: (+4 -4) ScheduleDAG.cpp |4 ++-- ScheduleDAGRRList.cpp |4 ++-- 2 files changed, 4 in

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGISel.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAGISel.h updated: 1.26 -> 1.27 --- Log message: Start checking from the root of the matched sub-tree. --- Diffs of the changes: (+2 -2) SelectionDAGISel.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/in

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.270 -> 1.271 --- Log message: When checking if a load can be folded, we check if there is any non-direct way to reach the load via any nodes that would be folded. Start from the root of the matched sub-tree. --- Diffs of