Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.24 -> 1.25
X86InstrInfo.h updated: 1.50 -> 1.51
---
Log message:
ImmMask should be 3 for a two-bit field; Compact X86II
---
Diffs of the changes: (+3 -4)
X86.td |2 +-
X86InstrInfo.h |5 ++---
2 files changed, 3 ins
Changes in directory llvm/lib/VMCore:
Module.cpp updated: 1.66 -> 1.67
---
Log message:
Fix some think-o's in my last commit. Thanks to Chris for pointing them out.
---
Diffs of the changes: (+18 -16)
Module.cpp | 34 ++
1 files changed, 18 insertions(+),
Changes in directory llvm/lib/VMCore:
Module.cpp updated: 1.65 -> 1.66
---
Log message:
Change Module to use TargetData-compatible strings internally.
This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 .
---
Diffs of the changes: (+60 -1)
Module.cpp | 61
Changes in directory llvm/include/llvm:
Module.h updated: 1.71 -> 1.72
---
Log message:
Change Module to use TargetData-compatible strings internally.
This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 .
---
Diffs of the changes: (+5 -6)
Module.h | 11 +--
Changes in directory llvm/lib/Target/Sparc:
Sparc.td updated: 1.12 -> 1.13
SparcRegisterInfo.cpp updated: 1.43 -> 1.44
SparcRegisterInfo.h updated: 1.12 -> 1.13
---
Log message:
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
---
Diffs of the changes: (+16 -3)
Sparc.td
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.23 -> 1.24
X86RegisterInfo.cpp updated: 1.153 -> 1.154
X86RegisterInfo.h updated: 1.38 -> 1.39
---
Log message:
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
---
Diffs of the changes: (+28 -7)
X86.td
Changes in directory llvm/lib/Target/PowerPC:
PPC.td updated: 1.16 -> 1.17
PPCRegisterInfo.cpp updated: 1.66 -> 1.67
PPCRegisterInfo.h updated: 1.14 -> 1.15
---
Log message:
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
---
Diffs of the changes: (+71 -9)
PPC.td
Changes in directory llvm/lib/Target/IA64:
IA64.td updated: 1.8 -> 1.9
IA64RegisterInfo.cpp updated: 1.19 -> 1.20
IA64RegisterInfo.h updated: 1.7 -> 1.8
---
Log message:
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
---
Diffs of the changes: (+19 -60)
IA64.td
Changes in directory llvm/lib/Target/Alpha:
Alpha.td updated: 1.10 -> 1.11
AlphaRegisterInfo.cpp updated: 1.44 -> 1.45
AlphaRegisterInfo.h updated: 1.12 -> 1.13
---
Log message:
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
---
Diffs of the changes: (+31 -11)
Alpha.t
Changes in directory llvm/lib/Target/ARM:
ARM.td updated: 1.2 -> 1.3
ARMRegisterInfo.cpp updated: 1.1 -> 1.2
ARMRegisterInfo.h updated: 1.1 -> 1.2
---
Log message:
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
---
Diffs of the changes: (+15 -3)
ARM.td |
Changes in directory llvm/lib/Target:
Target.td updated: 1.82 -> 1.83
---
Log message:
Remove CalleeSavedRegisters from class Target.
---
Diffs of the changes: (+0 -4)
Target.td |4
1 files changed, 4 deletions(-)
Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.66 -> 1.67
CodeGenTarget.h updated: 1.27 -> 1.28
RegisterInfoEmitter.cpp updated: 1.42 -> 1.43
---
Log message:
Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.
---
Diffs of the changes: (+0 -40)
Cod
Changes in directory llvm/test/Regression/ExecutionEngine:
hello2.ll updated: 1.2 -> 1.3
---
Log message:
This test is buggy: printf is a varargs function. This fixes the test with
the PPC JIT
---
Diffs of the changes: (+2 -2)
hello2.ll |4 ++--
1 files changed, 2 insertions(+), 2 del
Changes in directory llvm/lib:
Makefile updated: 1.21 -> 1.22
---
Log message:
Make some changes suggested by Chris:
1. Remove the LLVM_DO_NOT_BUILD feature (not needed any more)
2. Ensure that lib/VMCore gets built first. This needs to be done because
VMCore now uses tblgen to generate the
Changes in directory llvm:
Makefile updated: 1.58 -> 1.59
Makefile.rules updated: 1.369 -> 1.370
---
Log message:
Make some changes suggested by Chris:
1. Remove the LLVM_DO_NOT_BUILD feature (not needed any more)
2. Ensure that lib/VMCore gets built first. This needs to be done because
VMCo
Changes in directory llvm/lib/Target:
TargetData.cpp updated: 1.64 -> 1.65
---
Log message:
Fix a stupid bug when parsing TargetData strings.
---
Diffs of the changes: (+3 -1)
TargetData.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetData.cp
Changes in directory llvm/lib:
Makefile updated: 1.20 -> 1.21
---
Log message:
Use DIRS here instead of PARALLEL_DIRS, as VMCore has to be built before the
other dirs (for Intrinsics.gen). :(
---
Diffs of the changes: (+2 -2)
Makefile |4 ++--
1 files changed, 2 insertions(+), 2 delet
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.105 -> 1.106
---
Log message:
Another entry
---
Diffs of the changes: (+9 -0)
README.txt |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.105
l
Changes in directory llvm/lib/Target/Alpha:
Alpha.td updated: 1.9 -> 1.10
---
Log message:
Remove PointerType from class Target
---
Diffs of the changes: (+0 -3)
Alpha.td |3 ---
1 files changed, 3 deletions(-)
Index: llvm/lib/Target/Alpha/Alpha.td
diff -u llvm/lib/Target/Alpha/Alpha.
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.267 -> 1.268
---
Log message:
Use generic iPTR instead i32 to represent pointer type.
---
Diffs of the changes: (+3 -3)
X86InstrInfo.td |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Targ
Changes in directory llvm/tools:
Makefile updated: 1.46 -> 1.47
---
Log message:
Remove the llvm-db and bugpoint restrictions from the win32 platform so
they can be compiled with ming32. The use of fork(2) has been removed.
---
Diffs of the changes: (+1 -11)
Makefile | 12 +---
1
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.22 -> 1.23
---
Log message:
Remove PointerType from class Target
---
Diffs of the changes: (+0 -3)
X86.td |3 ---
1 files changed, 3 deletions(-)
Index: llvm/lib/Target/X86/X86.td
diff -u llvm/lib/Target/X86/X86.td:1.22 llvm/
Changes in directory llvm/lib/Target/IA64:
IA64.td updated: 1.7 -> 1.8
---
Log message:
Remove PointerType from class Target
---
Diffs of the changes: (+0 -4)
IA64.td |4
1 files changed, 4 deletions(-)
Index: llvm/lib/Target/IA64/IA64.td
diff -u llvm/lib/Target/IA64/IA64.td:1.7
Changes in directory llvm/lib/Target/PowerPC:
PPC.td updated: 1.15 -> 1.16
---
Log message:
Remove PointerType from class Target
---
Diffs of the changes: (+0 -3)
PPC.td |3 ---
1 files changed, 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC.td
diff -u llvm/lib/Target/PowerPC/PPC.t
Changes in directory llvm/lib/Target/Sparc:
Sparc.td updated: 1.11 -> 1.12
---
Log message:
Remove PointerType from class Target
---
Diffs of the changes: (+0 -3)
Sparc.td |3 ---
1 files changed, 3 deletions(-)
Index: llvm/lib/Target/Sparc/Sparc.td
diff -u llvm/lib/Target/Sparc/Sparc
Changes in directory llvm/lib/Target:
Target.td updated: 1.81 -> 1.82
---
Log message:
Remove PointerType from class Target
---
Diffs of the changes: (+0 -4)
Target.td |4
1 files changed, 4 deletions(-)
Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.81 llvm
Changes in directory llvm/lib/Target/ARM:
ARM.td updated: 1.1 -> 1.2
---
Log message:
Remove PointerType from class Target
---
Diffs of the changes: (+0 -3)
ARM.td |3 ---
1 files changed, 3 deletions(-)
Index: llvm/lib/Target/ARM/ARM.td
diff -u llvm/lib/Target/ARM/ARM.td:1.1 llvm/lib
Changes in directory llvm/lib/Transforms/Scalar:
LowerAllocations.cpp updated: 1.57 -> 1.58
LowerInvoke.cpp updated: 1.35 -> 1.36
LowerSelect.cpp updated: 1.5 -> 1.6
LowerSwitch.cpp updated: 1.20 -> 1.21
Mem2Reg.cpp updated: 1.16 -> 1.17
---
Log message:
Declare that lowerinvoke doesn't interac
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.65 -> 1.66
---
Log message:
Typo
---
Diffs of the changes: (+2 -2)
CodeGenTarget.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGe
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.246 -> 1.247
---
Log message:
Fix the result of the call to use a correct vbitconvert. There is no need to
use getPackedTypeBreakdown at all here.
---
Diffs of the changes: (+8 -23)
SelectionDAGISel.cpp |
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.245 -> 1.246
---
Log message:
Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll
---
Diffs of the changes: (+5 -18)
SelectionDAGISel.cpp | 23 +--
1 files changed, 5 inse
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.64 -> 1.65
CodeGenTarget.h updated: 1.26 -> 1.27
DAGISelEmitter.cpp updated: 1.203 -> 1.204
DAGISelEmitter.h updated: 1.63 -> 1.64
---
Log message:
Remove PointerType from target definition. Use abstract type MVT::iPTR to
re
Changes in directory llvm/test/Regression/ExecutionEngine:
2005-12-02-TailCallBug.ll updated: 1.3 -> 1.4
---
Log message:
PR736: http://llvm.cs.uiuc.edu/PR736 has already been fixed. Remove XFAIL
marker.
---
Diffs of the changes: (+0 -3)
2005-12-02-TailCallBug.ll |3 ---
1 files chan
Changes in directory llvm/test/Regression/CodeGen/X86:
2006-05-17-VectorArg.ll added (r1.1)
---
Log message:
New test case for vector type argument pass by value.
---
Diffs of the changes: (+14 -0)
2006-05-17-VectorArg.ll | 14 ++
1 files changed, 14 insertions(+)
Index: ll
Changes in directory llvm/lib/Target/Alpha:
AlphaRegisterInfo.cpp updated: 1.43 -> 1.44
---
Log message:
Fix call_adj.ll
---
Diffs of the changes: (+1 -1)
AlphaRegisterInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
dif
Changes in directory llvm/lib/Target/Alpha:
AlphaAsmPrinter.cpp updated: 1.42 -> 1.43
---
Log message:
Added sanity check for obviously bogus immediates
---
Diffs of the changes: (+1 -0)
AlphaAsmPrinter.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/Alpha/AlphaAsmPri
Changes in directory llvm/test/Regression/CodeGen/Alpha:
call_adj.ll added (r1.1)
---
Log message:
Added regression that breaks gcc4 build
---
Diffs of the changes: (+15 -0)
call_adj.ll | 15 +++
1 files changed, 15 insertions(+)
Index: llvm/test/Regression/CodeGen/Alpha/cal
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.205 -> 1.206
X86ISelLowering.h updated: 1.61 -> 1.62
---
Log message:
Should pass by reference.
---
Diffs of the changes: (+4 -4)
X86ISelLowering.cpp |4 ++--
X86ISelLowering.h |4 ++--
2 files changed, 4 ins
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.104 -> 1.105
---
Log message:
Another entry
---
Diffs of the changes: (+12 -0)
README.txt | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.1
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.91 -> 1.92
---
Log message:
Add a note about a note
---
Diffs of the changes: (+4 -0)
README.txt |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/REA
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.186 -> 1.187
PPCISelLowering.cpp updated: 1.179 -> 1.180
PPCISelLowering.h updated: 1.49 -> 1.50
PPCInstrInfo.td updated: 1.219 -> 1.220
---
Log message:
Make PPC call lowering more aggressive, making the isel matching
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.65 -> 1.66
---
Log message:
Another typo. Pointed out by Nate Begeman.
---
Diffs of the changes: (+1 -1)
TargetLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/TargetLowering.c
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.74 -> 1.75
---
Log message:
Another typo. Pointed out by Nate Begeman.
---
Diffs of the changes: (+1 -1)
TargetLowering.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/Target/Ta
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.244 -> 1.245
---
Log message:
Fixed a LowerCallTo and LowerArguments bug. They were introducing illegal
VBIT_VECTOR nodes. There were some confusion about the semantics of
getPackedTypeBreakdown(). e.g. for <4
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.64 -> 1.65
---
Log message:
Fix an obvious bug in getPackedTypeBreakdown. Return 1 if type is legal.
---
Diffs of the changes: (+2 -2)
TargetLowering.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.73 -> 1.74
---
Log message:
Fix a mis-leading comment.
---
Diffs of the changes: (+1 -1)
TargetLowering.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/Target/TargetLowering.h
d
Changes in directory llvm/include/llvm/Transforms/Utils:
Cloning.h updated: 1.18 -> 1.19
---
Log message:
Add a CloneModule call that exposes the mapping of values from the old module
to the new module. Patch provided by Nick Lewycky!
---
Diffs of the changes: (+1 -0)
Cloning.h |1 +
Changes in directory llvm/lib/Transforms/Utils:
CloneModule.cpp updated: 1.17 -> 1.18
---
Log message:
Add a CloneModule call that exposes the mapping of values from the old module
to the new module. Patch provided by Nick Lewycky!
---
Diffs of the changes: (+8 -4)
CloneModule.cpp | 12
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.376 -> 1.377
---
Log message:
When we legalize target nodes, do not use getNode to create a new node,
use UpdateNodeOperands to just update the operands! This is important because
getNode will allocate a new node if
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.375 -> 1.376
---
Log message:
Add an assertion, avoid some unneeded work for each call. No functionality
change.
---
Diffs of the changes: (+10 -6)
LegalizeDAG.cpp | 16 ++--
1 files changed, 10 i
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