Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.2 -> 1.3
---
Log message:
Add more SSE intrinsics
---
Diffs of the changes: (+118 -94)
IntrinsicsX86.td | 212 ++-
1 files changed, 118 insertions(+), 94 deletions(-)
I
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.77 -> 1.78
---
Log message:
Another entry about shuffles.
---
Diffs of the changes: (+6 -0)
README.txt |6 ++
1 files changed, 6 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.142 -> 1.143
X86InstrSSE.td updated: 1.41 -> 1.42
---
Log message:
- More shuffle related bug fixes.
- Whenever possible use ops of the right packed types for vector shuffles /
splats.
---
Diffs of the changes: (+30 -
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.141 -> 1.142
X86InstrSSE.td updated: 1.40 -> 1.41
---
Log message:
- Only use pshufd for v4i32 vector shuffles.
- Other shuffle related fixes.
---
Diffs of the changes: (+83 -61)
X86ISelLowering.cpp | 51 +++
Changes in directory llvm/lib/Target/PowerPC:
README_ALTIVEC.txt updated: 1.5 -> 1.6
---
Log message:
add a note
---
Diffs of the changes: (+4 -0)
README_ALTIVEC.txt |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/Po
Changes in directory llvm/test/Regression/CodeGen/Generic:
vector-constantexpr.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+10 -0)
vector-constantexpr.ll | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/test/Regression/CodeGen/Generic/vector-c
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.211 -> 1.212
---
Log message:
Bug fixes: handle constantexpr insert/extract element operations
Handle constantpacked vectors with constantexpr elements.
This fixes CodeGen/Generic/vector-constantexpr.ll
---
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.39 -> 1.40
---
Log message:
Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics.
The source operands type are v4sf with upper bits passes through.
Added matching code for these.
---
Diffs of the chan
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.140 -> 1.141
---
Log message:
Fixing buggy code.
---
Diffs of the changes: (+6 -6)
X86ISelLowering.cpp | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering
Changes in directory llvm/utils/TableGen:
IntrinsicEmitter.cpp updated: 1.16 -> 1.17
---
Log message:
Don't sort the names before outputing the intrinsic name table. It causes a
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.132 -> 1.133
---
Log message:
When building a VVECTOR_SHUFFLE node from extract_element operations, make
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).
The later is not canonical form, and pre
Changes in directory llvm-test/SingleSource/UnitTests/Vector/Altivec:
casts.c added (r1.1)
---
Log message:
Random testcase from my collection
---
Diffs of the changes: (+30 -0)
casts.c | 30 ++
1 files changed, 30 insertions(+)
Index: llvm-test/SingleSource
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.131 -> 1.132
---
Log message:
Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y')
---
Diffs of the changes: (+30 -0)
DAGCombiner.cpp | 30 ++
1 files changed, 30 inse
Changes in directory llvm/test/Regression/CodeGen/X86:
unpcklps.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+18 -0)
unpcklps.ll | 18 ++
1 files changed, 18 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/unpcklps.ll
diff -c /dev/null
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.130 -> 1.131
---
Log message:
Turn a series of extract_element's feeding a build_vector into a
vector_shuffle node. For this:
void test(__m128 *res, __m128 *A, __m128 *B) {
*res = _mm_unpacklo_ps(*A, *B);
}
we n
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.341 -> 1.342
---
Log message:
Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes.
---
Diffs of the changes: (+21 -0)
LegalizeDAG.cpp | 21 +
1 files changed, 21 inse
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.291 -> 1.292
---
Log message:
new node
---
Diffs of the changes: (+1 -0)
SelectionDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeG
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.124 -> 1.125
---
Log message:
Add a new node
---
Diffs of the changes: (+9 -0)
SelectionDAGNodes.h |9 +
1 files changed, 9 insertions(+)
Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.129 -> 1.130
---
Log message:
Don't crash on X^X if X is a vector. Instead, produce a vector of zeros.
---
Diffs of the changes: (+10 -2)
DAGCombiner.cpp | 12 ++--
1 files changed, 10 insertions(+),
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.290 -> 1.291
---
Log message:
Add an assertion
---
Diffs of the changes: (+2 -0)
SelectionDAG.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm
Changes in directory llvm/lib/Target/PowerPC:
README_ALTIVEC.txt updated: 1.4 -> 1.5
---
Log message:
add a note
---
Diffs of the changes: (+10 -0)
README_ALTIVEC.txt | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/T
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.52 -> 1.53
---
Log message:
Refactor address attributes. Add base register to frame info.
---
Diffs of the changes: (+19 -13)
DwarfWriter.cpp | 32 +++-
1 files changed, 19 insertions(+), 13 de
Changes in directory llvm/include/llvm/CodeGen:
DwarfWriter.h updated: 1.31 -> 1.32
---
Log message:
Refactor address attributes. Add base register to frame info.
---
Diffs of the changes: (+5 -0)
DwarfWriter.h |5 +
1 files changed, 5 insertions(+)
Index: llvm/include/llvm/Code
Changes in directory llvm/lib/Target/SparcV9:
SparcV9RegisterInfo.cpp updated: 1.11 -> 1.12
SparcV9RegisterInfo.h updated: 1.10 -> 1.11
---
Log message:
Expose base register for DwarfWriter. Refactor code accordingly.
---
Diffs of the changes: (+5 -4)
SparcV9RegisterInfo.cpp |4 ++--
Changes in directory llvm/lib/Target/Alpha:
AlphaRegisterInfo.cpp updated: 1.38 -> 1.39
AlphaRegisterInfo.h updated: 1.10 -> 1.11
---
Log message:
Expose base register for DwarfWriter. Refactor code accordingly.
---
Diffs of the changes: (+4 -12)
AlphaRegisterInfo.cpp | 12 ++--
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.51 -> 1.52
PPCRegisterInfo.h updated: 1.11 -> 1.12
---
Log message:
Expose base register for DwarfWriter. Refactor code accordingly.
---
Diffs of the changes: (+4 -11)
PPCRegisterInfo.cpp | 11 ++-
PPCR
Changes in directory llvm/lib/Target/Sparc:
SparcRegisterInfo.cpp updated: 1.39 -> 1.40
SparcRegisterInfo.h updated: 1.10 -> 1.11
---
Log message:
Expose base register for DwarfWriter. Refactor code accordingly.
---
Diffs of the changes: (+4 -11)
SparcRegisterInfo.cpp | 11 ++-
Changes in directory llvm/lib/Target:
MRegisterInfo.cpp updated: 1.12 -> 1.13
---
Log message:
Expose base register for DwarfWriter. Refactor code accordingly.
---
Diffs of the changes: (+16 -0)
MRegisterInfo.cpp | 16
1 files changed, 16 insertions(+)
Index: llvm/lib
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.132 -> 1.133
X86RegisterInfo.h updated: 1.35 -> 1.36
---
Log message:
Expose base register for DwarfWriter. Refactor code accordingly.
---
Diffs of the changes: (+4 -11)
X86RegisterInfo.cpp | 11 ++-
X86Reg
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.72 -> 1.73
---
Log message:
Expose base register for DwarfWriter. Refactor code accordingly.
---
Diffs of the changes: (+11 -1)
MRegisterInfo.h | 12 +++-
1 files changed, 11 insertions(+), 1 deletion(-)
Changes in directory llvm/lib/Target/IA64:
IA64RegisterInfo.cpp updated: 1.15 -> 1.16
IA64RegisterInfo.h updated: 1.5 -> 1.6
---
Log message:
Expose base register for DwarfWriter. Refactor code accordingly.
---
Diffs of the changes: (+4 -12)
IA64RegisterInfo.cpp | 13 ++---
IA64
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.210 -> 1.211
---
Log message:
More bulletproofing of llvm.dbg.declare.
---
Diffs of the changes: (+1 -1)
SelectionDAGISel.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Code
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.139 -> 1.140
---
Log message:
Added missing paren on behalf of Ramana Radhakrishnan.
---
Diffs of the changes: (+1 -1)
X86ISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Ta
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.138 -> 1.139
---
Log message:
Missed X86::isUNPCKHMask
---
Diffs of the changes: (+2 -1)
X86ISelLowering.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
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