[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.td

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.31 -> 1.32 X86InstrInfo.td updated: 1.198 -> 1.199 --- Log message: * Materialize GlobalAddress and ExternalSym with MOV32ri rather than LEA32r. * Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it. --

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.131 -> 1.132 --- Log message: GlobalAddress -> TargetGlobalAddress; ExternalSymbol -> TargetExternalSymbol --- Diffs of the changes: (+14 -2) DAGISelEmitter.cpp | 16 ++-- 1 files changed, 14 insertions(+

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.46 -> 1.47 --- Log message: fix a bug in my previous checkin --- Diffs of the changes: (+3 -2) SparcV8ISelDAGToDAG.cpp |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Sp

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.45 -> 1.46 --- Log message: Give V8ISD nodes symbolic names in dumps --- Diffs of the changes: (+18 -0) SparcV8ISelDAGToDAG.cpp | 18 ++ 1 files changed, 18 insertions(+) Index: llvm/lib/Ta

[llvm-commits] CVS: llvm/lib/VMCore/Verifier.cpp

Changes in directory llvm/lib/VMCore: Verifier.cpp updated: 1.137 -> 1.138 --- Log message: Convert the verifier over to use ETForest instead of DominatorSet. Patch by Daniel Berlin --- Diffs of the changes: (+14 -14) Verifier.cpp | 28 ++-- 1 files changed, 14 i

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp

Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.17 -> 1.18 --- Log message: sabre's (correct) fix means these guys need to be flagged as well (else the scheduler will complain) --- Diffs of the changes: (+7 -2) IA64ISelLowering.cpp |9 +++-- 1 files chan

[llvm-commits] CVS: llvm/test/Regression/CodeGen/SparcV8/xnor.ll

Changes in directory llvm/test/Regression/CodeGen/SparcV8: xnor.ll updated: 1.1 -> 1.2 --- Log message: verily, sabre did leave and yea! Saem said "ARRR." meanwhile, the pinksias and the campfires and the ET forests glowed. --- Diffs of the changes: (+2 -2) xnor.ll |4 ++-- 1 files

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.173 -> 1.174 --- Log message: ahem :) --- Diffs of the changes: (+1 -1) PPCInstrInfo.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Targe

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.148 -> 1.149 --- Log message: remove dead code --- Diffs of the changes: (+2 -25) PPCISelDAGToDAG.cpp | 27 ++- 1 files changed, 2 insertions(+), 25 deletions(-) Index: llvm/lib/Target/

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.149 -> 1.150 --- Log message: these cases are autogenerated --- Diffs of the changes: (+0 -28) PPCISelDAGToDAG.cpp | 28 1 files changed, 28 deletions(-) Index: llvm/lib/Target/Pow

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.h PPCTargetMachine.cpp PPCISelPattern.cpp

Changes in directory llvm/lib/Target/PowerPC: PPC.h updated: 1.24 -> 1.25 PPCTargetMachine.cpp updated: 1.78 -> 1.79 PPCISelPattern.cpp (r1.194) removed --- Log message: Goodbye PPC pattern isel. You have served us well, but it is now time for you to ride off into the sunset. --- Diffs of th

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp

Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.16 -> 1.17 --- Log message: Fix an itanium call lowering bug for duraid --- Diffs of the changes: (+6 -6) IA64ISelLowering.cpp | 12 ++-- 1 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/lib/

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8TargetMachine.cpp updated: 1.34 -> 1.35 --- Log message: invert the sense of this switch and its name --- Diffs of the changes: (+4 -4) SparcV8TargetMachine.cpp |8 1 files changed, 4 insertions(+), 4 deletions(-) Index: l

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp

Changes in directory llvm/lib/Target/IA64: IA64ISelPattern.cpp updated: 1.73 -> 1.74 --- Log message: Missed a spot. --- Diffs of the changes: (+2 -0) IA64ISelPattern.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp diff -u llvm/lib/Target/I

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.39 -> 1.40 --- Log message: If a function has a non-zero sized frame, use an add to adjust the stack pointer in the epilog, not a load. --- Diffs of the changes: (+20 -9) PPCRegisterInfo.cpp | 29 ++

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.td

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.30 -> 1.31 X86InstrInfo.td updated: 1.197 -> 1.198 --- Log message: Added ROTL and ROTR. --- Diffs of the changes: (+64 -30) X86ISelLowering.cpp | 14 + X86InstrInfo.td | 80 +++

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.41 -> 1.42 --- Log message: Fix an off-by-one error that Nate's eagle eyes caught --- Diffs of the changes: (+1 -1) PPCRegisterInfo.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/T

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.40 -> 1.41 --- Log message: Use the auto-insert BuildMI constructor to avoid an explicit insert. No functionality change, just code cleanup. --- Diffs of the changes: (+20 -28) PPCRegisterInfo.cpp | 48

[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/rotl.ll

Changes in directory llvm/test/Regression/CodeGen/PowerPC: rotl.ll added (r1.1) --- Log message: Add testcase for rotate by register and rotate by immediate --- Diffs of the changes: (+51 -0) rotl.ll | 51 +++ 1 files changed, 51 insertions

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.236 -> 1.237 --- Log message: ignore register #0 --- Diffs of the changes: (+1 -1) SelectionDAG.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.29 -> 1.30 --- Log message: Select DYNAMIC_STACKALLOC --- Diffs of the changes: (+44 -1) X86ISelDAGToDAG.cpp | 45 - 1 files changed, 44 insertions(+), 1 deletion(-) Ind

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86ISelPattern.cpp X86InstrInfo.td

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.29 -> 1.30 X86ISelLowering.h updated: 1.13 -> 1.14 X86ISelPattern.cpp updated: 1.193 -> 1.194 X86InstrInfo.td updated: 1.196 -> 1.197 --- Log message: Support for MEMCPY and MEMSET. --- Diffs of the changes: (+137 -10)

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.259 -> 1.260 --- Log message: Allow custom lowering of DYNAMIC_STACKALLOC. --- Diffs of the changes: (+20 -7) LegalizeDAG.cpp | 27 --- 1 files changed, 20 insertions(+), 7 deletions(-)

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.130 -> 1.131 --- Log message: Some minor fixes. --- Diffs of the changes: (+19 -26) DAGISelEmitter.cpp | 45 +++-- 1 files changed, 19 insertions(+), 26 deletions(-) Index: l

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.28 -> 1.29 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the changes: (+7

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp

Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.18 -> 1.19 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the changes:

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.44 -> 1.45 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the chang

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.79 -> 1.80 LegalizeDAG.cpp updated: 1.258 -> 1.259 SelectionDAG.cpp updated: 1.235 -> 1.236 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl T

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.62 -> 1.63 PPCInstrInfo.td updated: 1.172 -> 1.173 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if the

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp

Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.15 -> 1.16 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the changes: (

[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td

Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.42 -> 1.43 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the changes: (+2 -

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.88 -> 1.89 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the changes

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.129 -> 1.130 --- Log message: Always select target registers to themselves --- Diffs of the changes: (+1 -0) DAGISelEmitter.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/utils/TableGen/DAGISelEmitter.cpp

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.61 -> 1.62 --- Log message: Fix calls that need to store values in stack slots, to not copy the stack pointer. This allows us to emit stuff like this: li r10, 0 stw r10, 56(r1) or r3, r10, r10

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.18 -> 1.19 --- Log message: tblgen does this now --- Diffs of the changes: (+0 -2) IA64ISelDAGToDAG.cpp |2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.43 -> 1.44 --- Log message: This is no longer needed --- Diffs of the changes: (+0 -1) SparcV8ISelDAGToDAG.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.60 -> 1.61 --- Log message: Dead FP arguments still use an incoming FP reg. This fixes Regression/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll, which was distilled from a miscompilation in 252.eon. --- Diffs

[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll

Changes in directory llvm/test/Regression/CodeGen/PowerPC: 2006-01-11-darwin-fp-argument.ll added (r1.1) --- Log message: Testcase the PPC backend is miscompiling. --- Diffs of the changes: (+13 -0) 2006-01-11-darwin-fp-argument.ll | 13 + 1 files changed, 13 insertions(+)

[llvm-commits] CVS: llvm/win32/VMCore/VMCore.vcproj

Changes in directory llvm/win32/VMCore: VMCore.vcproj updated: 1.11 -> 1.12 --- Log message: Visual Studio is feeling left out again. --- Diffs of the changes: (+12 -0) VMCore.vcproj | 12 1 files changed, 12 insertions(+) Index: llvm/win32/VMCore/VMCore.vcproj diff -u llvm

[llvm-commits] CVS: llvm/lib/VMCore/PassManagerT.h

Changes in directory llvm/lib/VMCore: PassManagerT.h updated: 1.65 -> 1.66 --- Log message: Patch #9 from Saem: "Cut up the runPasses method into smaller pieces. The small private helpers should be easier to deal with when code shuffling arising from creating the new specialised batchers, no

[llvm-commits] CVS: llvm/lib/VMCore/TypeSymbolTable.cpp

Changes in directory llvm/lib/VMCore: TypeSymbolTable.cpp updated: 1.2 -> 1.3 --- Log message: Fix VC++ compilation error. --- Diffs of the changes: (+1 -0) TypeSymbolTable.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/VMCore/TypeSymbolTable.cpp diff -u llvm/lib/VMCore/Typ