Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.6 -> 1.7
AlphaISelLowering.cpp updated: 1.9 -> 1.10
AlphaISelLowering.h updated: 1.3 -> 1.4
AlphaISelPattern.cpp updated: 1.188 -> 1.189
AlphaInstrFormats.td updated: 1.14 -> 1.15
AlphaInstrInfo.td updated: 1.73 -> 1.74
Changes in directory llvm-test:
Makefile.programs updated: 1.179 -> 1.180
---
Log message:
Why not. Performance sucks, but correctness sucks more, so sounds just right
for beta. Maybe I will be surprised.
---
Diffs of the changes: (+2 -2)
Makefile.programs |4 ++--
1 files changed, 2
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.217 -> 1.218
---
Log message:
add support for custom lowering SINT_TO_FP
---
Diffs of the changes: (+13 -0)
LegalizeDAG.cpp | 13 +
1 files changed, 13 insertions(+)
Index: llvm/lib/CodeGen/Select
Changes in directory llvm/docs:
index.html updated: 1.47 -> 1.48
---
Log message:
Add a link to the doxygen tarball
---
Diffs of the changes: (+5 -2)
index.html |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
Index: llvm/docs/index.html
diff -u llvm/docs/index.html:1.47
Changes in directory llvm/docs:
Makefile updated: 1.10 -> 1.11
---
Log message:
copy the doxygen tarball into the HTML directory after building it
---
Diffs of the changes: (+1 -0)
Makefile |1 +
1 files changed, 1 insertion(+)
Index: llvm/docs/Makefile
diff -u llvm/docs/Makefile:1.
Changes in directory llvm/include/llvm/Bytecode:
Archive.h updated: 1.12 -> 1.13
---
Log message:
minor cleanup
---
Diffs of the changes: (+1 -1)
Archive.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/Bytecode/Archive.h
diff -u llvm/include/llvm/Byte
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.106 -> 1.107
---
Log message:
Fix a problem with llvm-ranlib that (on some platforms) caused the archive
file to become corrupted due to interactions between mmap'd memory segments
and file descriptors closing.
Changes in directory llvm/lib/Bytecode/Archive:
Archive.cpp updated: 1.9 -> 1.10
ArchiveWriter.cpp updated: 1.20 -> 1.21
---
Log message:
Fix a problem with llvm-ranlib that (on some platforms) caused the archive
file to become corrupted due to interactions between mmap'd memory segments
and fi
Changes in directory llvm/include/llvm/Bytecode:
Archive.h updated: 1.11 -> 1.12
---
Log message:
Fix a problem with llvm-ranlib that (on some platforms) caused the archive
file to become corrupted due to interactions between mmap'd memory segments
and file descriptors closing. The problem is c
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.142 -> 1.143
---
Log message:
Fix a bug in a recent patch that broke shifts
---
Diffs of the changes: (+3 -3)
X86InstrInfo.td |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X8
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.3 -> 1.4
---
Log message:
Added support to STORE and shifts to DAG to DAG isel.
---
Diffs of the changes: (+88 -8)
X86ISelDAGToDAG.cpp | 96 +++-
1 files changed, 88 i
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.217 -> 1.218
---
Log message:
Fixed a bug introduced by my last commit: TargetGlobalValues should key on
GlobalValue * and index pair. Update getGlobalAddress() for symmetry.
---
Diffs of the changes: (+13 -7)
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.72 -> 1.73
---
Log message:
Fixed a bug introduced by my last commit: TargetGlobalValues should key on
GlobalValue * and index pair. Update getGlobalAddress() for symmetry.
---
Diffs of the changes: (+5 -4)
Selection
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.45 -> 1.46
SelectionDAG.cpp updated: 1.216 -> 1.217
SelectionDAGPrinter.cpp updated: 1.29 -> 1.30
---
Log message:
Added an index field to GlobalAddressSDNode so it can represent X+12, etc.
---
Diffs of the changes
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.71 -> 1.72
SelectionDAGNodes.h updated: 1.79 -> 1.80
---
Log message:
Added an index field to GlobalAddressSDNode so it can represent X+12, etc.
---
Diffs of the changes: (+25 -2)
SelectionDAG.h |6 +-
S
Changes in directory llvm/lib/Target/X86:
X86IntelAsmPrinter.cpp updated: 1.11 -> 1.12
---
Log message:
Fixed a minor bug: - -offset != offset iff offset == MININT
---
Diffs of the changes: (+1 -1)
X86IntelAsmPrinter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: ll
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.58 -> 1.59
PPCInstrInfo.td updated: 1.146 -> 1.147
---
Log message:
Represent the encoding of the SPR instructions as they actually are, so
that we can use the correct SPR numbers in the InstrInfo.td file. This is
nece
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.76 -> 1.77
---
Log message:
Better error message when unrecognized opcode is seen.
---
Diffs of the changes: (+6 -1)
DAGISelEmitter.cpp |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm/util
Changes in directory llvm-gcc/gcc:
llvm-expand.c updated: 1.117 -> 1.118
llvm-representation.c updated: 1.20 -> 1.21
llvm-representation.h updated: 1.19 -> 1.20
---
Log message:
Allow switch statements on long-long values to be correctly handled. This
fixes PR671: http://llvm.cs.uiuc.edu/PR671
Changes in directory llvm-test/SingleSource/UnitTests:
2005-11-29-LongSwitch.c added (r1.1)
---
Log message:
new testcase corresponding to PR671: http://llvm.cs.uiuc.edu/PR671
---
Diffs of the changes: (+19 -0)
2005-11-29-LongSwitch.c | 19 +++
1 files changed, 19 insert
On Tue, 29 Nov 2005, Andrew Lenharth wrote:
Add the majority of the vector machien value types we expect to support,
and make a few changes to the legalization machinery to support more than
16 types.
Just in case anyone cares, the relevant vector types for alpha are:
v8i8, v4i16, and maybe v2
> Add the majority of the vector machien value types we expect to support,
> and make a few changes to the legalization machinery to support more than
> 16 types.
Just in case anyone cares, the relevant vector types for alpha are:
v8i8, v4i16, and maybe v2i32 (only one unpack operation produces t
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.46 -> 1.47
---
Log message:
Hook up one type, v4f32, to the VR RegisterClass for now.
---
Diffs of the changes: (+6 -0)
PPCISelLowering.cpp |6 ++
1 files changed, 6 insertions(+)
Index: llvm/lib/Target/
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.57 -> 1.58
PPCInstrInfo.td updated: 1.145 -> 1.146
---
Log message:
Add the remainder of the AltiVec 4 x float instructions. Further
enhancements will be necessary to teach the code generator that since
there is no fmu
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