[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.404 -> 1.405 --- Log message: Turn sdiv into udiv if both operands have a clear sign bit. This occurs a few times in crafty: OLD:%tmp.36 = div int %tmp.35, 8; [#uses=1] NEW:%tmp.36 = div

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.403 -> 1.404 --- Log message: Turn srem -> urem when neither input has their sign bit set. This triggers 8 times in vortex, allowing the srems to be turned into shrs: OLD:%tmp.104 = rem int %tmp.5.i37, 16

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.41 -> 1.42 --- Log message: Fix logic bug in finding retry slot in tally. --- Diffs of the changes: (+33 -15) ScheduleDAG.cpp | 48 +--- 1 files changed, 33 insertio

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.40 -> 1.41 --- Log message: Fix a warning --- Diffs of the changes: (+1 -0) ScheduleDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp diff -u llvm/lib/CodeGe

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.7 -> 1.8 --- Log message: oops, forgot to load GP for indirect calls, though the old code now commented out failed (e.g. methcall) - now the code compiles, though it's not quite right just yet (tm) ;) would fix this but

[llvm-commits] [release_16] CVS: llvm-gcc/gcc/llvm-types.c

Changes in directory llvm-gcc/gcc: llvm-types.c updated: 1.30 -> 1.30.2.1 --- Log message: Merged in revision 1.31. --- Diffs of the changes: (+39 -3) llvm-types.c | 42 +++--- 1 files changed, 39 insertions(+), 3 deletions(-) Index: llvm-gcc/gcc/llv

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp

Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.2 -> 1.3 --- Log message: kill redundant SP/GP/RP save/restores across calls --- Diffs of the changes: (+3 -2) IA64ISelLowering.cpp |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/lib/T

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.6 -> 1.7 --- Log message: add support for loading bools --- Diffs of the changes: (+7 -1) IA64ISelDAGToDAG.cpp |8 +++- 1 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/lib/Target/IA64/IA64ISel