https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 78ffc92ec65935c16caedc8ac3f9943e544c7dcd Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From f563ccef965406f4df3a4481142795de32e596f4 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 8801c5d2a09a59313acc26da52c1b6383369f624 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
@@ -69,11 +82,295 @@ FunctionPass *llvm::createAMDGPURegBankLegalizePass() {
return new AMDGPURegBankLegalize();
}
-using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ stat
@@ -69,11 +82,295 @@ FunctionPass *llvm::createAMDGPURegBankLegalizePass() {
return new AMDGPURegBankLegalize();
}
-using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ stat
@@ -106,3 +106,59 @@ void IntrinsicLaneMaskAnalyzer::findLCSSAPhi(Register Reg)
{
S32S64LaneMask.insert(LCSSAPhi.getOperand(0).getReg());
}
}
+
+static LLT getReadAnyLaneSplitTy(LLT Ty) {
+ if (Ty.isVector()) {
+LLT ElTy = Ty.getElementType();
+if (ElTy == LLT
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From d3f746c12fc0e741dfe754f19f394d770a22e84c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 0adced1346e563e75aab408c2a948cdbd8c449c3 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 23 Jan 2025 13:35:07 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From d3f746c12fc0e741dfe754f19f394d770a22e84c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/124298
Record all uses outside cycle with divergent exit during
propagateTemporalDivergence in Uniformity analysis.
With this list of candidates for temporal divergence lowering,
excluding known lane masks from
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/124299?utm_source=stack-comment-downstack-mergeability-w
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/124298?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic ready_for_review
https://github.com/llvm/llvm-project/pull/124298
___
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https://github.com/petar-avramovic ready_for_review
https://github.com/llvm/llvm-project/pull/124299
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https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 73554e86fc276e15db22462749aa71324d1e1f41 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From c336fe428d4d1824a4a437c99655cb909bf328c6 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 87c8fc15b5b8ccb0b7d48065caa82cdbeddfeac5 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 87c8fc15b5b8ccb0b7d48065caa82cdbeddfeac5 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 8cb73f44dd58c897ad3acde5e29014a21ea38ea4 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 23 Jan 2025 13:35:07 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 0030251f71c08000c1b4ff123cc401b70c72014f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 23 Jan 2025 13:35:07 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 23bb343f473f02b014efb83c5ec4aee9fc41c611 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From 45cec5fb9bb567d759b71963b9109c770c222a89 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefVa
@@ -9,7 +9,11 @@
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
+#include "AMDGPURegisterBankInfo.h"
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/ADT/DenseSet.h"
+#include "llvm/CodeGen/GlobalISel/
https://github.com/petar-avramovic ready_for_review
https://github.com/llvm/llvm-project/pull/132382
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petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/132382?utm_source=stack-comment-downstack-mergeability-w
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/132383?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/132383
Uniform S1:
Truncs to uniform S1 and AnyExts from S1 are left as is as they are meant
to be combined away. Uniform S1 ZExt and SExt are lowered using select.
Divergent S1:
Trunc of VGPR to VCC is lowered
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/132385
Uniform S16 shifts have to be extended to S32 using appropriate Extend
before lowering to S32 instruction.
Uniform packed V2S16 are lowered to SGPR S32 instructions,
other option is to use VALU packed V2S
https://github.com/petar-avramovic ready_for_review
https://github.com/llvm/llvm-project/pull/132385
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https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From fdca6f36c330e482508359c45557b07c45c7b898 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:44:20 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for exten
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 4e74a7e91e4b8638b30f3bd13437b7a149e7a1a1 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:42:48 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND O
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/132385?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic edited
https://github.com/llvm/llvm-project/pull/132383
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https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 4e74a7e91e4b8638b30f3bd13437b7a149e7a1a1 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:42:48 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND O
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 55cb190188c7202057c9275447f46eecaea10153 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:44:20 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for exten
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 0572a36a99cc3ab39de8e4f06a1ff37c29c2a53f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 15:22:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 54ff03532148bfc48ace062e453eaad8ec74fdda Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:42:48 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND O
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 0572a36a99cc3ab39de8e4f06a1ff37c29c2a53f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 15:22:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 55cb190188c7202057c9275447f46eecaea10153 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:44:20 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for exten
@@ -489,22 +489,61 @@ RegBankLegalizeRules::RegBankLegalizeRules(const
GCNSubtarget &_ST,
.Uni(B32, {{SgprB32}, {Sgpr32AExtBoolInReg, SgprB32, SgprB32}});
addRulesForGOpcs({G_ANYEXT})
+ .Any({{UniS16, S1}, {{None}, {None}}}) // should be combined away
.Any
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/132384?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From c7a043e7c0a4e8b76bafdd6a2f6ad84066d19953 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 15:22:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From c7a043e7c0a4e8b76bafdd6a2f6ad84066d19953 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 15:22:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From fdca6f36c330e482508359c45557b07c45c7b898 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:44:20 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for exten
@@ -492,7 +511,8 @@ LLT
RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) {
case UniInVgprB64:
if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(0, 64) ||
-Ty == LLT:
petar-avramovic wrote:
> Does this also handle the test cases in `regbankselect-and-s1.mir` ?
It requires some rules for extends, enabled it in the next patch. However I had
to edit tests a little, uniform s1 has to be used by something.
https://github.com/llvm/llvm-project/pull/132382
___
@@ -179,8 +174,7 @@ body: |
; CHECK: liveins: $sgpr0
petar-avramovic wrote:
[Re: line
+159]
> This change is a code quality regression: the input has G_ANYEXT, so the high
> half can be undefined.
fixed
See this comment
inline on https://app.graphite.dev
@@ -215,8 +207,8 @@ body: |
; CHECK: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
-; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
-; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 2fdf172213d449b78bc6de1ac20d493adda29dbc Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From c57e5228d3143ea83920086bb8a994d1b00a74c5 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:34:00 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for exten
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From c57e5228d3143ea83920086bb8a994d1b00a74c5 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:34:00 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for exten
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From ba48a1abb1b10c2f77f9acd137150cfa59de7601 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:32:49 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND O
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 2fdf172213d449b78bc6de1ac20d493adda29dbc Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 61c28d2d564c63b986c6adfae26f17d868b53cd1 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:34:00 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for exten
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 61c28d2d564c63b986c6adfae26f17d868b53cd1 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:34:00 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for exten
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 585448f8cf5f77c26c63c5b1dc126bec85a5ff53 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 5cc4f822aafd00eb4c88a76dadd07b716904ad97 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:32:49 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND O
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 585448f8cf5f77c26c63c5b1dc126bec85a5ff53 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 5cc4f822aafd00eb4c88a76dadd07b716904ad97 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:32:49 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND O
@@ -1390,29 +927,17 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
-; FAST-LABEL: name: select_p999_scc_ss
-; FAST: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
-; FAST-NEXT: {{ $}}
-; FAST-NEXT: [[COPY:%[0-9]+
@@ -341,9 +328,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) =
G_UNMERGE_VALUES [[COPY]](s64)
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) =
G_UNME
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 183f6cc9a037bed5f472be13e32f39002520 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 183f6cc9a037bed5f472be13e32f39002520 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 915bee3729c66b327885838c6384d14f92c2af2d Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
Rate limit ยท GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Aria
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From f084882197a92f537c38ec19dfabdafdd9f15d09 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:56:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/128702
>From c844e3ac372ec27d57c6d5aad3567426a460936f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:54:55 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Update divergence lowering tests
I
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From f084882197a92f537c38ec19dfabdafdd9f15d09 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:56:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/128702
>From c844e3ac372ec27d57c6d5aad3567426a460936f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:54:55 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Update divergence lowering tests
I
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From 31f4387623100e815d478245ca78b6dcc52f869e Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:56:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/128702
>From 8e33358f5f3ca6167cc585acb7661d7a5f4a8568 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:54:55 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Update divergence lowering tests
I
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/128702
>From 8e33358f5f3ca6167cc585acb7661d7a5f4a8568 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:54:55 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Update divergence lowering tests
I
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From 31f4387623100e815d478245ca78b6dcc52f869e Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:56:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From 4afb1c71ac30cf952fc48c7f92abfa012a0c4efa Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:56:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From 9a5bfd368f40d1c313dc1783df4f43f12b88258b Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:56:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From 3f039f909b91cc5ad1f92208944e0b66447346df Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 21 Feb 2025 14:33:44 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
@@ -188,6 +190,35 @@ void
DivergenceLoweringHelper::constrainAsLaneMask(Incoming &In) {
In.Reg = Copy.getReg(0);
}
+void replaceUsesOfRegInInstWith(Register Reg, MachineInstr *Inst,
+Register NewReg) {
+ for (MachineOperand &Op : Inst->opera
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From a637e5612bfe21aa7e71209ac05924309ffc9fe5 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 21 Feb 2025 14:33:44 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
@@ -188,6 +190,35 @@ void
DivergenceLoweringHelper::constrainAsLaneMask(Incoming &In) {
In.Reg = Copy.getReg(0);
}
+void replaceUsesOfRegInInstWith(Register Reg, MachineInstr *Inst,
+Register NewReg) {
+ for (MachineOperand &Op : Inst->opera
@@ -188,6 +190,35 @@ void
DivergenceLoweringHelper::constrainAsLaneMask(Incoming &In) {
In.Reg = Copy.getReg(0);
}
+void replaceUsesOfRegInInstWith(Register Reg, MachineInstr *Inst,
+Register NewReg) {
+ for (MachineOperand &Op : Inst->opera
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From 538c0b43558d091886b844c8a1603e83d7aaf864 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 31 Jan 2025 13:04:17 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
https://github.com/petar-avramovic ready_for_review
https://github.com/llvm/llvm-project/pull/128702
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https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/128702
In preparations for implementing temporal divergence lowering for
global-isel, switch llvm-ir tests for amdgpu divergence lowering
to new reg bank select. Requires adding few simple regbanklegalize
rules
https://github.com/petar-avramovic edited
https://github.com/llvm/llvm-project/pull/124298
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petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/128702?utm_source=stack-comment-downstack-mergeability-w
@@ -234,45 +225,47 @@ define amdgpu_cs void
@single_lane_execution_attribute(i32 inreg %.userdata0, <3
; GFX10-NEXT:s_mov_b32 s1, 0
; GFX10-NEXT:v_mbcnt_lo_u32_b32 v1, -1, 0
; GFX10-NEXT:s_or_b64 s[12:13], s[4:5], s[0:1]
-; GFX10-NEXT:s_mov_b32 s3, -1
; GFX10-
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 54ff03532148bfc48ace062e453eaad8ec74fdda Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:42:48 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND O
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/132382
Uniform S1 is lowered to S32.
Divergent S1 is selected as VCC(S1) instruction select will select
SALU instruction based on wavesize (S32 or S64).
S16 are selected as is. There are register classes for vgp
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 9f92e94f7171f9e04405dee69b0f69ea80fbeb2f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 21 Mar 2025 13:12:11 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic ready_for_review
https://github.com/llvm/llvm-project/pull/132383
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@@ -489,22 +489,61 @@ RegBankLegalizeRules::RegBankLegalizeRules(const
GCNSubtarget &_ST,
.Uni(B32, {{SgprB32}, {Sgpr32AExtBoolInReg, SgprB32, SgprB32}});
addRulesForGOpcs({G_ANYEXT})
+ .Any({{UniS16, S1}, {{None}, {None}}}) // should be combined away
.Any
https://github.com/petar-avramovic edited
https://github.com/llvm/llvm-project/pull/132383
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@@ -13,7 +12,8 @@ body: |
; CHECK: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
-; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[COPY]](s32)
+; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+
@@ -233,8 +222,13 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
-; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[TRUN
@@ -251,8 +245,11 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
-; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUN
@@ -269,10 +266,12 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
-; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRU
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From e6b6d99ef184920dbc418b7fd8b545b5c6ed59c7 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:02:27 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 915bee3729c66b327885838c6384d14f92c2af2d Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
@@ -32,6 +32,7 @@ class RegBankLegalizeHelper {
const MachineUniformityInfo &MUI;
const RegisterBankInfo &RBI;
const RegBankLegalizeRules &RBLRules;
+ const bool IsWave32;
petar-avramovic wrote:
you mean this?
https://github.com/llvm/llvm-project/pull/
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