https://github.com/JoshdRod updated
https://github.com/llvm/llvm-project/pull/170832
>From 7e897eac1eee87148b1f3529a42e4b927b556d44 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez
Date: Thu, 27 Nov 2025 15:34:40 +
Subject: [PATCH 1/9] [AArch64][GlobalISel] Removed fallback for sqshlu
intrins
https://github.com/JoshdRod created
https://github.com/llvm/llvm-project/pull/170832
Many neon right shift intrinsics were not supported by GlobalISel, mainly due
to a lack of legalisation logic. This logic has now been implemented.
>From 7e897eac1eee87148b1f3529a42e4b927b556d44 Mon Sep 17 00:
https://github.com/JoshdRod updated
https://github.com/llvm/llvm-project/pull/170832
>From 74f88e80b88b68d8058fb7171803a2147f2b1a78 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez
Date: Thu, 27 Nov 2025 15:34:40 +
Subject: [PATCH 1/9] [AArch64][GlobalISel] Removed fallback for sqshlu
intrins
https://github.com/JoshdRod updated
https://github.com/llvm/llvm-project/pull/170832
>From 74f88e80b88b68d8058fb7171803a2147f2b1a78 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez
Date: Thu, 27 Nov 2025 15:34:40 +
Subject: [PATCH 1/9] [AArch64][GlobalISel] Removed fallback for sqshlu
intrins
https://github.com/JoshdRod updated
https://github.com/llvm/llvm-project/pull/171448
>From 7854c9af0229e0da243ae75cc08aa3d65c1bdc8c Mon Sep 17 00:00:00 2001
From: Josh Rodriguez
Date: Tue, 9 Dec 2025 14:27:56 +
Subject: [PATCH] [GlobalISel][AArch64] Added support for sli intrinsic
sli intr
https://github.com/JoshdRod created
https://github.com/llvm/llvm-project/pull/171448
sli intrinsic now lowers correctly for all vector types.
>From 2045520c433183c633ff5ea84e8708b8a37cec51 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez
Date: Tue, 9 Dec 2025 14:27:56 +
Subject: [PATCH] [Glob
https://github.com/JoshdRod updated
https://github.com/llvm/llvm-project/pull/171448
>From b1591d7b90292a562771510067a99eb22bc629c9 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez
Date: Tue, 9 Dec 2025 14:27:56 +
Subject: [PATCH] [GlobalISel][AArch64] Added support for sli intrinsic
sli intr
@@ -270,6 +270,12 @@ def G_URSHR: AArch64GenericInstruction {
let hasSideEffects = 0;
}
+def G_VSLI: AArch64GenericInstruction {
JoshdRod wrote:
There's an SRI that isn't supported yet - should I also add a test case to this
file?
https://github.com/llvm/
https://github.com/JoshdRod updated
https://github.com/llvm/llvm-project/pull/171448
>From 7854c9af0229e0da243ae75cc08aa3d65c1bdc8c Mon Sep 17 00:00:00 2001
From: Josh Rodriguez
Date: Tue, 9 Dec 2025 14:27:56 +
Subject: [PATCH 1/5] [GlobalISel][AArch64] Added support for sli intrinsic
sli
https://github.com/JoshdRod edited
https://github.com/llvm/llvm-project/pull/171448
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