[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

https://github.com/walter-erquinigo approved this pull request. https://github.com/llvm/llvm-project/pull/109495 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [NVPTX] add address class for variables with a single register location (PR #110030)

https://github.com/walter-erquinigo approved this pull request. amazing https://github.com/llvm/llvm-project/pull/110030 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch

[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

@@ -141,3 +142,47 @@ NVPTXRegisterInfo::getFrameLocalRegister(const MachineFunction &MF) const { static_cast(MF.getTarget()); return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32; } + +void NVPTXRegisterInfo::clearDebugRegisterMap() const { + debugRegis

[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

@@ -1773,6 +1774,26 @@ void NVPTXAsmPrinter::setAndEmitFunctionVirtualRegisters( OutStreamer->emitRawText(O.str()); } +/// Translate virtual register numbers in DebugInfo locations to their printed +/// encodings, as used by CUDA-GDB. +void NVPTXAsmPrinter::encodeDebugInfoRe

[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

@@ -141,3 +142,47 @@ NVPTXRegisterInfo::getFrameLocalRegister(const MachineFunction &MF) const { static_cast(MF.getTarget()); return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32; } + +void NVPTXRegisterInfo::clearDebugRegisterMap() const { + debugRegis

[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

@@ -141,3 +142,47 @@ NVPTXRegisterInfo::getFrameLocalRegister(const MachineFunction &MF) const { static_cast(MF.getTarget()); return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32; } + +void NVPTXRegisterInfo::clearDebugRegisterMap() const { + debugRegis

[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

@@ -141,3 +142,47 @@ NVPTXRegisterInfo::getFrameLocalRegister(const MachineFunction &MF) const { static_cast(MF.getTarget()); return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32; } + +void NVPTXRegisterInfo::clearDebugRegisterMap() const { + debugRegis

[llvm-branch-commits] [lldb] 4bb6244 - [ThreadPlan] fix exec on Linux

Author: Walter Erquinigo Date: 2021-01-25T11:30:48-08:00 New Revision: 4bb6244871c6914517a21f56830b3765495792f2 URL: https://github.com/llvm/llvm-project/commit/4bb6244871c6914517a21f56830b3765495792f2 DIFF: https://github.com/llvm/llvm-project/commit/4bb6244871c6914517a21f56830b3765495792f2.di

[llvm-branch-commits] [lldb] 39239f9 - [lldb-vscode] improve modules request

Author: Walter Erquinigo Date: 2021-01-21T13:18:50-08:00 New Revision: 39239f9b5666bebb059fa562badeffb9f1c3afab URL: https://github.com/llvm/llvm-project/commit/39239f9b5666bebb059fa562badeffb9f1c3afab DIFF: https://github.com/llvm/llvm-project/commit/39239f9b5666bebb059fa562badeffb9f1c3afab.di

[llvm-branch-commits] [lldb] fcd1604 - [lldb-vscode] support the completion request

Author: Walter Erquinigo Date: 2019-11-15T15:49:32-08:00 New Revision: fcd1604ccdd0acba6ca8a31a2ee7fa0b465fbccb URL: https://github.com/llvm/llvm-project/commit/fcd1604ccdd0acba6ca8a31a2ee7fa0b465fbccb DIFF: https://github.com/llvm/llvm-project/commit/fcd1604ccdd0acba6ca8a31a2ee7fa0b465fbccb.di