[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148108 >From 837ec7b0b82b939d87000bf12b7e22705c1c31b7 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:00:55 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Read TargetMachine's EnableIPRA option --- llvm

[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148109 >From 24e03050c25d4c480e8e4540452495a908aca29b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:03:19 +0530 Subject: [PATCH] [CodeGen][NPM] Register Function Passes --- .../llvm/Passes/Machin

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 358f2e2b2aa99ce56ac8d24ff4d88cfa9bcb2327 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include

[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From 3fc8b6ea10eb633a208cedbe21656d3fe95698ee Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/

[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148111 >From 245b1cd1df9bb2cae6d36428d30c4578fea0fd8b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:24:23 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Account inserted passes for -start/stop options

[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148113 >From 6b203cd5f6d6786dc2ddf8c5fb0e20b004c80c9b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:50:27 +0530 Subject: [PATCH] [CodeGen][NPM] Clear MachineFunctions without using PA --- .../llv

[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148109 >From 24e03050c25d4c480e8e4540452495a908aca29b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:03:19 +0530 Subject: [PATCH] [CodeGen][NPM] Register Function Passes --- .../llvm/Passes/Machin

[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148108 >From 837ec7b0b82b939d87000bf12b7e22705c1c31b7 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:00:55 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Read TargetMachine's EnableIPRA option --- llvm

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148112 >From fdd06a88e3a53f98fe3eaba9d70e1cf8913e Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:26:16 +0530 Subject: [PATCH] [AMDGPU][NPM] Fill in addPreSched2 passes --- llvm/lib/Target/AMDG

[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From 3fc8b6ea10eb633a208cedbe21656d3fe95698ee Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148112 >From fdd06a88e3a53f98fe3eaba9d70e1cf8913e Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:26:16 +0530 Subject: [PATCH] [AMDGPU][NPM] Fill in addPreSched2 passes --- llvm/lib/Target/AMDG

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 358f2e2b2aa99ce56ac8d24ff4d88cfa9bcb2327 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include

[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148113 >From 6b203cd5f6d6786dc2ddf8c5fb0e20b004c80c9b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:50:27 +0530 Subject: [PATCH] [CodeGen][NPM] Clear MachineFunctions without using PA --- .../llv

[llvm-branch-commits] [llvm] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag (PR #148107)

https://github.com/vikramRH edited https://github.com/llvm/llvm-project/pull/148107 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Port ProcessImplicitDefs to NPM (PR #148110)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)

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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag (PR #148107)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Port ProcessImplicitDefs to NPM (PR #148110)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)

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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)

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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag (PR #148107)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Port ProcessImplicitDefs to NPM (PR #148110)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)

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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)

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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Port ProcessImplicitDefs to NPM (PR #148110)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag (PR #148107)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148113?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148111?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148115?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148114?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148109?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)

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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148112?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Port ProcessImplicitDefs to NPM (PR #148110)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148110?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] Port ProcessImplicitDefs to NPM (PR #148110)

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[llvm-branch-commits] [llvm] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag (PR #148107)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148107?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148108?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag (PR #148107)

https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/148107 None >From a7b5f3a39a9f65757d1659eaca8ddf410cf6aa45 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 15:25:03 +0530 Subject: [PATCH] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag --- llvm/in

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)

vikramRH wrote: > > > > [AMDGPU] Enable atomic optimizer for divergent i64 and double values > > > > > > > > > Needs some i64 tests > > > > > > added new i64 tests, however I see there currently exists an issue with DPP > > path where dpp combine partially fuses the mov_dpp pieces causing ma

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)

vikramRH wrote: > > [AMDGPU] Enable atomic optimizer for divergent i64 and double values > > Needs some i64 tests added new i64 tests, however I see there currently exists an issue with DPP path where dpp combine partially fuses the mov_dpp pieces causing machine CSE crash. I have proposed ht

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)

@@ -178,6 +178,21 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { return Changed; } +static bool isOptimizableAtomic(Type *Ty) { vikramRH wrote: updated, thanks https://github.com/llvm/llvm-project/pull/96934 _

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)

@@ -230,8 +245,7 @@ void AMDGPUAtomicOptimizerImpl::visitAtomicRMWInst(AtomicRMWInst &I) { // value to the atomic calculation. We can only optimize divergent values if // we have DPP available on our subtarget, and the atomic operation is 32 // bits. - if (ValDivergent

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)

@@ -178,6 +178,21 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { return Changed; } +static bool isOptimizableAtomic(Type *Ty) { + switch (Ty->getTypeID()) { + case Type::FloatTyID: + case Type::DoubleTyID: +return true; + case Type::IntegerTyID: { +unsigne

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)

@@ -178,6 +178,20 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { return Changed; } +static bool shouldOptimizeForType(Type *Ty) { + switch (Ty->getTypeID()) { + case Type::FloatTyID: + case Type::DoubleTyID: +return true; + case Type::IntegerTyID: { +if (T

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)

@@ -178,6 +178,20 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { return Changed; } +static bool shouldOptimizeForType(Type *Ty) { + switch (Ty->getTypeID()) { + case Type::FloatTyID: + case Type::DoubleTyID: +return true; + case Type::IntegerTyID: { +if (T

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for divergent i64 and double values (PR #96934)

https://github.com/vikramRH edited https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for 64 bit divergent values (PR #96934)

@@ -178,6 +178,20 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { return Changed; } +static bool shouldOptimizeForType(Type *Ty) { vikramRH wrote: Any better suggestions ? https://github.com/llvm/llvm-project/pull/96934 __

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for 64 bit divergent values (PR #96934)

https://github.com/vikramRH ready_for_review https://github.com/llvm/llvm-project/pull/96934 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Enable atomic optimizer for 64 bit divergent values (PR #96934)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/96934?utm_source=stack-comment-downstack-mergeability-warning";