@@ -447,14 +447,42 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N,
unsigned RegClassID) {
return;
}
+ bool IsGCN = CurDAG->getSubtarget().getTargetTriple().isAMDGCN();
+ if (IsGCN && Subtarget->has64BitLiterals() && VT.getSizeInBits() == 64 &&
+ CurDAG->
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> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148057?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/148057
None
>From 10f072f90c8c575c670a7ad50c8f8531144a27d3 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 10 Jul 2025 13:47:02 -0700
Subject: [PATCH] [AMDGPU] Negative gfx1250 v_dual_cndmask_b32 test
rampitec wrote:
I know github does not help. This is the example change:
```
v_dual_add_f32 v255, s105, v2 :: v_dual_add_f32 v7, s1, v3
// GFX1250: v_dual_add_f32 v255, s105, v2 :: v_dual_add_f32 v7, s1, v3 ;
encoding: [0x69,0x40,0x10,0xcf,0x01,0x00,0x02,0x00,0xff,0x03,0x00,0x07]
-// W64-ERR:
@@ -9937,3 +9937,6339 @@ v_dual_mul_f32 v255, -1, v4 :: v_dual_subrev_f32 v6,
src_scc, v5
v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
// GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456,
v4 ; encoding: [0x7c,0x0a,0xcc,0xc8,0xff
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/147918?utm_source=stack-comment-downstack-mergeability-warning"
@@ -9937,3 +9937,6339 @@ v_dual_mul_f32 v255, -1, v4 :: v_dual_subrev_f32 v6,
src_scc, v5
v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
// GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456,
v4 ; encoding: [0x7c,0x0a,0xcc,0xc8,0xff
rampitec wrote:
> Not sure what's "overflow" about these
Joe asked to split the test because github does not show long files in the web
interface. I have just cut it around ~1 lines so it is shown for review.
https://github.com/llvm/llvm-project/pull/147826
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> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/147826?utm_source=stack-comment-downstack-mergeability-warning"
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@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx1250 -show-mc-encoding -verify-machineinstrs
< %s | FileCheck -check-prefix=GFX1250 %s
rampitec wrote:
Will do. This is a very old
@@ -9669,6 +9670,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
+ if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts())
rampitec wrote:
0x means it is already a real opcode. 0x means it is n
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rampitec wrote:
Actually the first codegen test for the subtarget.
https://github.com/llvm/llvm-project/pull/145152
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145152?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/145152
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>From ae162ef51dd115f68c86cce893a0ae7baf99e6b9 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Fri, 20 Jun 2025 12:24:47 -0700
Subject: [PATCH] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction
https://github.com/rampitec commented:
Do you assume that at this stage there are no accvgpr_write/read instructions,
but only COPY?
https://github.com/llvm/llvm-project/pull/145024
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/143430?utm_source=stack-comment-downstack-mergeability-warning"
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/143429?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/143430
None
>From 1d58dc465ebd0049e9f4d6b9c32b65b72b88be3e Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 9 Jun 2025 12:47:55 -0700
Subject: [PATCH] [AMDGPU] Autogenerate bitop3 asm and dags. NFCI.
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/143429
Needed for future t16 support.
>From 3c462dc48271923cf466e0e0c2c86f26bb69eb11 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 9 Jun 2025 11:53:11 -0700
Subject: [PATCH] [AMDGPU] Autogenerate ds
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142911
>From c8524591999f495dd86261daecc44071737a227b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:49:43 -0700
Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs)
---
llv
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142910
>From 641fb5022daeca9b71527e18ea2df7982856a105 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:46:28 -0700
Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC.
---
ll
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142911
>From c8524591999f495dd86261daecc44071737a227b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:49:43 -0700
Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs)
---
llv
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142910
>From 641fb5022daeca9b71527e18ea2df7982856a105 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:46:28 -0700
Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC.
---
ll
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/142911
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142910?utm_source=stack-comment-downstack-mergeability-warning"
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142911?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/142911
None
>From 44a9017e98eff94456889a528a166d6aabca842d Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:49:43 -0700
Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs)
--
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/142910
None
>From 321eb42ae21d0d3156fb5ef15f5b336551a20c5b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:46:28 -0700
Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC.
-
@@ -1835,6 +1835,11 @@ def : GCNPat <
(S_XOR_B32 SReg_32:$src, (S_MOV_B32 (i32 0x80008000)))
>;
+def : GCNPat <
rampitec wrote:
Done
https://github.com/llvm/llvm-project/pull/142870
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142870
>From 80608a949bf530cf77faa7dac7dd1a2f9aa357c1 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 15:37:20 -0700
Subject: [PATCH] [AMDGPU] Make <2 x bfloat> fneg legal
---
llvm/lib/Tar
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142870
>From 80608a949bf530cf77faa7dac7dd1a2f9aa357c1 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 15:37:20 -0700
Subject: [PATCH] [AMDGPU] Make <2 x bfloat> fneg legal
---
llvm/lib/Tar
@@ -1835,6 +1835,11 @@ def : GCNPat <
(S_XOR_B32 SReg_32:$src, (S_MOV_B32 (i32 0x80008000)))
>;
+def : GCNPat <
rampitec wrote:
I can. But fabs needs the same, so for now it will be isolated.
https://github.com/llvm/llvm-project/pull/142870
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142870?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/142870
None
>From 27a5d3f0d06f1fc9efe6ed482c5ace394faff88e Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 15:37:20 -0700
Subject: [PATCH] [AMDGPU] Make <2 x bfloat> fneg legal
---
llvm/l
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https://github.com/llvm/llvm-project/pull/142176
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LGTM with a nit: title says it is legal, but it is custom.
https://github.com/llvm/llvm-project/pull/142173
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@@ -704,8 +704,29 @@ static bool intrinsicHasPackedVectorBenefit(Intrinsic::ID
ID) {
InstructionCost
GCNTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind) const {
- if (ICA.getID() == Intrinsic::f
@@ -704,8 +704,29 @@ static bool intrinsicHasPackedVectorBenefit(Intrinsic::ID
ID) {
InstructionCost
GCNTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind) const {
- if (ICA.getID() == Intrinsic::f
https://github.com/rampitec approved this pull request.
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LGTM
https://github.com/llvm/llvm-project/pull/140582
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/140155?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
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None
>From 071898b2e2b1f23e67ad5471df2088a0db167555 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 15 May 2025 15:41:55 -0700
Subject: [PATCH] [AMDGPU] Automate creation of byte_sel dags. NFCI
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/139531
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LGTM
https://github.com/llvm/llvm-project/pull/139137
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LGTM, although I do not see practical improvements in the tests.
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@@ -11,11 +10,9 @@ define amdgpu_kernel void @ptr_nest_3(ptr addrspace(1)
nocapture readonly %Arg)
; CHECK-NEXT: entry:
; CHECK-NEXT:[[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT:[[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1)
[[ARG:%.
@@ -11,11 +10,9 @@ define amdgpu_kernel void @ptr_nest_3(ptr addrspace(1)
nocapture readonly %Arg)
; CHECK-NEXT: entry:
; CHECK-NEXT:[[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT:[[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1)
[[ARG:%.
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/115090
>From f7e10b1e26159442945c2682ca1ed463bd152605 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Nov 2024 12:28:07 -0800
Subject: [PATCH] [AMDGPU] Simplify dpp builtin handling
DPP intrinsics c
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/115090
>From f7e10b1e26159442945c2682ca1ed463bd152605 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Nov 2024 12:28:07 -0800
Subject: [PATCH] [AMDGPU] Simplify dpp builtin handling
DPP intrinsics c
https://github.com/rampitec approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/129059
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/127142
>From b574a4b4afbf4cd0a6e128ea5d1e1579698124bc Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 13 Feb 2025 14:46:37 -0800
Subject: [PATCH] [AMDGPU] Respect MBB alignment in the getFunctionCodeSi
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/127142
>From b574a4b4afbf4cd0a6e128ea5d1e1579698124bc Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 13 Feb 2025 14:46:37 -0800
Subject: [PATCH] [AMDGPU] Respect MBB alignment in the getFunctionCodeSi
rampitec wrote:
And in any case it is a moot until baseline change is accepted.
https://github.com/llvm/llvm-project/pull/127142
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rampitec wrote:
> > Which one do you prefer, this or #127246? They are mutually exclusive.
>
> They're not really. This one is the incremental step which adds the test,
> #127246 is the final form
The test is meaningless if we overestimate.
https://github.com/llvm/llvm-project/pull/127142
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https://github.com/rampitec approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/127485
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https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/127483
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rampitec wrote:
Which one do you prefer, this or
https://github.com/llvm/llvm-project/pull/127246? They are mutually exclusive.
https://github.com/llvm/llvm-project/pull/127142
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ht
rampitec wrote:
> There is also MF.estimateFunctionSizeInBytes(), probably should use that as a
> stop gap until MC computes this
https://github.com/llvm/llvm-project/pull/127246
For some reason it is not const and also can overestimate code size.
https://github.com/llvm/llvm-project/pull/127
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/127246
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/127246?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/127246
Both methods are equally inaccurate, we need to switch to MCExpr
for better results in the future.
>From 99b5a597f7a888269ebdbd0f054d6511b2c9950b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Fri,
@@ -212,6 +212,8 @@ uint64_t SIProgramInfo::getFunctionCodeSize(const
MachineFunction &MF) {
uint64_t CodeSize = 0;
for (const MachineBasicBlock &MBB : MF) {
+CodeSize = alignTo(CodeSize, MBB.getAlignment());
rampitec wrote:
Thanks. Added comment.
h
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/127142
>From 63e9a995b61b17c2fe064ca4142c58e541688cf4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 13 Feb 2025 14:46:37 -0800
Subject: [PATCH] [AMDGPU] Respect MBB alignment in the getFunctionCodeSi
@@ -212,6 +212,8 @@ uint64_t SIProgramInfo::getFunctionCodeSize(const
MachineFunction &MF) {
uint64_t CodeSize = 0;
for (const MachineBasicBlock &MBB : MF) {
+CodeSize = alignTo(CodeSize, MBB.getAlignment());
rampitec wrote:
Pessimistic overestimate
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/127142
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@@ -199,3 +201,28 @@ const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID
CC,
return MCConstantExpr::create(0, Ctx);
}
+
+uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF) {
+ if (!CodeSizeInBytes.has_value()) {
+const GCNSubtarget &STM = MF.ge
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/127142?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/127142
None
>From d01d16815ade61a599b94bb18bc292e326767f15 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 13 Feb 2025 14:46:37 -0800
Subject: [PATCH] [AMDGPU] Respect MBB alignment in the getFunction
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/127129
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/127129?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/127129
It does not change the estimate because getInstSizeInBytes() already
returns 0 for meta instructions, but added a test and early bail.
>From c0489545755c98dc2f87ffcd83af929816643074 Mon Sep 17 00:00:00 2001
Fro
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/126981
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@@ -199,3 +201,28 @@ const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID
CC,
return MCConstantExpr::create(0, Ctx);
}
+
+uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF) {
+ if (!CodeSizeInBytes.has_value()) {
+const GCNSubtarget &STM = MF.ge
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