[llvm-branch-commits] [llvm] SPARC: Start moving runtime libcall config to tablegen (PR #147672)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/147672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] RuntimeLibcalls: Avoid adding ppcf128 calls to non-ppc targets (PR #147656)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/147656 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] RuntimeLibcalls: Avoid adding f80 calls to default set (PR #147658)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/147658 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] RuntimeLibcalls: Stop using defset for default calls (PR #147651)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/147651 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Fall back to separate sin and cos when softening sincos (PR #147468)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/147468 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [X86] Ignore NSW when DstSVT is i32 (#131755) (PR #147034)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/147034 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] MSP430: Move libcall CC setting to RuntimeLibcallsInfo (PR #146081)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/146081 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] RuntimeLibcalls: Associate calling convention with libcall impls (PR #144979)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/144979 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Lanai: Use TableGen to set libcall calling conventions (PR #146080)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/146080 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences (PR #146054)

https://github.com/RKSimon commented: Why DAG and not InstCombine for this? https://github.com/llvm/llvm-project/pull/146054 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-br

[llvm-branch-commits] [llvm] [SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (PR #145902)

@@ -720,18 +720,17 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits( unsigned Scale = NumDstEltBits / NumSrcEltBits; unsigned NumSrcElts = SrcVT.getVectorNumElements(); APInt DemandedSrcBits = APInt::getZero(NumSrcEltBits); - APInt DemandedSrcEl

[llvm-branch-commits] [llvm] [SelectionDAG] Deal with POISON for INSERT_VECTOR_ELT/INSERT_SUBVECTOR (part 2) (PR #143103)

@@ -1881,6 +1881,11 @@ LLVM_ABI SDValue peekThroughExtractSubvectors(SDValue V); /// If \p V is not a truncation, it is returned as-is. LLVM_ABI SDValue peekThroughTruncates(SDValue V); +/// Recursively peek through INSERT_VECTOR_ELT nodes, returning the source +/// vector ope

[llvm-branch-commits] [llvm] [SelectionDAG] Deal with POISON for INSERT_VECTOR_ELT/INSERT_SUBVECTOR (part 2) (PR #143103)

@@ -1881,6 +1881,11 @@ LLVM_ABI SDValue peekThroughExtractSubvectors(SDValue V); /// If \p V is not a truncation, it is returned as-is. LLVM_ABI SDValue peekThroughTruncates(SDValue V); +/// Recursively peek through INSERT_VECTOR_ELT nodes, returning the source +/// vector ope

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)

https://github.com/RKSimon edited https://github.com/llvm/llvm-project/pull/120716 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)

https://github.com/RKSimon edited https://github.com/llvm/llvm-project/pull/120716 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)

@@ -1211,6 +1211,11 @@ def : Pat<(v4i32 (scalar_to_vector (i32 (atomic_load_32 addr:$src, def : Pat<(v2i64 (scalar_to_vector (i64 (atomic_load_64 addr:$src, (MOV64toPQIrm addr:$src)>; // load atomic <2 x i32,float> +def : Pat<(v2i64 (atomic_load_128_v2i64

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)

@@ -1211,6 +1211,11 @@ def : Pat<(v4i32 (scalar_to_vector (i32 (atomic_load_32 addr:$src, def : Pat<(v2i64 (scalar_to_vector (i64 (atomic_load_64 addr:$src, (MOV64toPQIrm addr:$src)>; // load atomic <2 x i32,float> +def : Pat<(v2i64 (atomic_load_128_v2i64

[llvm-branch-commits] [llvm] release/20.x: [SDAG] Ensure load is included in output chain of sincos expansion (#140525) (PR #140703)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/140703 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [X86] Remove extra MOV after widening atomic load (PR #138635)

@@ -1200,6 +1200,13 @@ def : Pat<(i16 (atomic_load_nonext_16 addr:$src)), (MOV16rm addr:$src)>; def : Pat<(i32 (atomic_load_nonext_32 addr:$src)), (MOV32rm addr:$src)>; def : Pat<(i64 (atomic_load_nonext_64 addr:$src)), (MOV64rm addr:$src)>; +def : Pat<(v4i32 (scalar_to_vecto

[llvm-branch-commits] [llvm] release/20.x: [X86][TargetLowering] Avoid deleting temporary nodes in `getNegatedExpression` (#139029) (PR #139356)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/139356 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [X86] Remove extra MOV after widening atomic load (PR #138635)

@@ -1200,6 +1200,13 @@ def : Pat<(i16 (atomic_load_nonext_16 addr:$src)), (MOV16rm addr:$src)>; def : Pat<(i32 (atomic_load_nonext_32 addr:$src)), (MOV32rm addr:$src)>; def : Pat<(i64 (atomic_load_nonext_64 addr:$src)), (MOV64rm addr:$src)>; +def : Pat<(v4i32 (scalar_to_vecto

[llvm-branch-commits] [llvm] [X86] Remove extra MOV after widening atomic load (PR #138635)

@@ -1200,6 +1200,13 @@ def : Pat<(i16 (atomic_load_nonext_16 addr:$src)), (MOV16rm addr:$src)>; def : Pat<(i32 (atomic_load_nonext_32 addr:$src)), (MOV32rm addr:$src)>; def : Pat<(i64 (atomic_load_nonext_64 addr:$src)), (MOV64rm addr:$src)>; +def : Pat<(v4i32 (scalar_to_vecto

[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)

https://github.com/RKSimon approved this pull request. LGTM with the clang-format warning fix https://github.com/llvm/llvm-project/pull/120385 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailma

[llvm-branch-commits] [clang] [llvm] release/20.x: [X86][AVX10] Remove VAES and VPCLMULQDQ feature from AVX10.1 (#135489) (PR #135577)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/135577 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-co

[llvm-branch-commits] [clang] [X86] Backport saturate-convert intrinsics renaming & YMM rounding intrinsics removal in AVX10.2 (PR #135549)

https://github.com/RKSimon approved this pull request. LGTM as a C/C++ intrinsics rename only cherry pick (the builtins were additionally renamed in trunk). https://github.com/llvm/llvm-project/pull/135549 ___ llvm-branch-commits mailing list llvm-bra

[llvm-branch-commits] [llvm] release/20.x: [X86][SSE] Don't emit SSE2 load instructions in SSE1-only mode (#134547) (PR #135191)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/135191 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [X86] Backport new intrinsic and instruction changes in AVX10.2 (PR #133219)

RKSimon wrote: > Doesn't this break ABI by changing intrinsic / builtin numbers? So the headers could still be updated but must use the existing builtins in the backport? https://github.com/llvm/llvm-project/pull/133219 ___ llvm-branch-commits mailin

[llvm-branch-commits] [llvm] [DAG][AArch64] Handle truncated buildvectors to allow and(subvector(anyext)) fold. (PR #133915)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/133915 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-co

[llvm-branch-commits] [llvm] [DAG][AArch64] Handle truncated buildvectors to allow and(subvector(anyext)) fold. (PR #133915)

@@ -7166,7 +7166,8 @@ SDValue DAGCombiner::visitAND(SDNode *N) { // if (and x, c) is known to be zero, return 0 unsigned BitWidth = VT.getScalarSizeInBits(); - ConstantSDNode *N1C = isConstOrConstSplat(N1); + ConstantSDNode *N1C = + isConstOrConstSplat(N1, /*AllowUn

[llvm-branch-commits] [clang] [llvm] [X86] Backport new intrinsic and instruction changes in AVX10.2 (PR #133219)

RKSimon wrote: Although these instructions aren't supported by current hardware this probably needs a release notes entry - wdyt? https://github.com/llvm/llvm-project/pull/133219 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] release/20.x: [X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824) (PR #132932)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/132932 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Fix promote of half freeze (PR #131844)

@@ -2763,7 +2763,10 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) { #endif report_fatal_error("Do not know how to promote this operator's result!"); -case ISD::BITCAST:R = PromoteFloatRes_BITCAST(N); break; +case ISD::BITCAST: +

[llvm-branch-commits] [llvm] release/20.x: [X86][AVX10.2] Fix unexpected larger scope (#130767) (PR #130774)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/130774 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (#129272) (PR #129383)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/129383 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [DAGCombiner] visitFREEZE: Early exit when N is deleted (#128161) (PR #128283)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/128283 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [X86] Do not combine LRINT and TRUNC (#125848) (PR #125995)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/125995 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Widen <2 x T> vector types for atomic load (PR #120598)

@@ -5907,6 +5910,91 @@ SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { N->getOperand(1), N->getOperand(2)); } +static std::optional findMemType(SelectionDAG &DAG, + const TargetLowering &TLI, unsig

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Split via Concat vector types for atomic load (PR #120640)

@@ -7071,14 +7071,23 @@ static SDValue LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, const SDLoc &dl, } // Recurse to find a LoadSDNode source and the accumulated ByteOffest. -static bool findEltLoadSrc(SDValue Elt, LoadSDNode *&Ld, int64_t &ByteOffset) { - if (ISD::isNON_EX

[llvm-branch-commits] [llvm] DAG: Avoid breaking legal vector_shuffle with multiple uses (PR #123712)

@@ -23172,6 +23172,11 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { } if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) { + // TODO: Check if shuffle mask is legal? + if (LegalOperations && TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VecVT) &&

[llvm-branch-commits] [llvm] DAG: Avoid forming shufflevector from a single extract_vector_elt (PR #122672)

@@ -23855,6 +23863,13 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) { // VecIn accordingly. bool DidSplitVec = false; if (VecIn.size() == 2) { RKSimon wrote: Thanks - it's been a while since I touched this code :) https://github.com/llvm/l

[llvm-branch-commits] [llvm] DAG: Avoid forming shufflevector from a single extract_vector_elt (PR #122672)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/122672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Avoid forming shufflevector from a single extract_vector_elt (PR #122672)

https://github.com/RKSimon edited https://github.com/llvm/llvm-project/pull/122672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Handle load in SimplifyDemandedVectorElts (PR #122671)

RKSimon wrote: X86TargetLowering::shouldReduceLoadWidth is a mess, resulting in a lot of duplicate aliasaed loads that make very little sense - we're seeing something similar on #122485, but it might take some time to unravel. https://github.com/llvm/llvm-project/pull/122671 __

[llvm-branch-commits] [llvm] DAG: Avoid forming shufflevector from a single extract_vector_elt (PR #122672)

@@ -23855,6 +23863,13 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) { // VecIn accordingly. bool DidSplitVec = false; if (VecIn.size() == 2) { RKSimon wrote: Doesn't this just check for 2 vector sources, not that there is a single extracti

[llvm-branch-commits] [llvm] DAG: Fold bitcast of scalar_to_vector to anyext (PR #122660)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/122660 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-co

[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)

@@ -2595,6 +2595,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(Op, MVT::f32, Promote); } + setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16); RKSimon wrote: Handle bf16 as well? https://g

[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/120387 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-co

[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)

@@ -110,3 +110,226 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) { ret <1 x bfloat> %ret } +define <1 x i64> @atomic_vec1_i64(ptr %x) { RKSimon wrote: add nounwind to get rid of cfi noise https://github.com/llvm/llvm-project/pull/120387 __

[llvm-branch-commits] [llvm] release/19.x: [VectorCombine] Do not try to operate on OperandBundles. (#111635) (PR #111796)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/111796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [VectorCombine] Do not try to operate on OperandBundles. (#111635) (PR #111796)

RKSimon wrote: @davemgreen The CI build failure is confusing - do OperandBundles occur in 19.x? https://github.com/llvm/llvm-project/pull/111796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/ma

[llvm-branch-commits] [llvm] [X86][APX] Fix wrong encoding of promoted KMOV instructions due to missing NoCD8 (#109579) (PR #109635)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/109635 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [compiler-rt] [llvm] [X86] AMD Zen 5 Initial enablement (PR #108816)

RKSimon wrote: LLVM Release Notes: ``` Changes to the X86 Backend -mcpu=znver5 is now supported. ``` Clang Release Notes: ``` X86 Support -march=znver5 is now supported ``` @ganeshgit Are you happy with this? https://github.com/llvm/llvm-project/pull/108816 __

[llvm-branch-commits] [clang] Backport "[Clang][CodeGen] Fix type for atomic float incdec operators (#107075)" (PR #107184)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/107184 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [compiler-rt] [llvm] [X86] AMD Zen 5 Initial enablement (PR #108816)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/108816 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] Backport "[Clang][CodeGen] Fix type for atomic float incdec operators (#107075)" (PR #107184)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/107184 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes (PR #100521)

https://github.com/RKSimon approved this pull request. LGTM - the x86 lowering needs reworking but that shouldn't hold this PR up. https://github.com/llvm/llvm-project/pull/100521 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] TTI: Check legalization cost of abs nodes (PR #100523)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/100523 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mul overflow ISD nodes (PR #100519)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/100519 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mulfix ISD nodes (PR #100520)

https://github.com/RKSimon approved this pull request. LGTM - although I don't think we have any legal/custom cost test coverage (only x86 which exapands) https://github.com/llvm/llvm-project/pull/100520 ___ llvm-branch-commits mailing list llvm-branc

[llvm-branch-commits] [llvm] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes (PR #100521)

RKSimon wrote: I'm not sure whether its better to just focus on removing some of the custom lowering (and improve TargetLowering::expandFP_TO_INT_SAT) or just add better cost table support. https://github.com/llvm/llvm-project/pull/100521 ___ llvm-br

[llvm-branch-commits] [llvm] TTI: Check legalization cost of min/max ISD nodes (PR #100514)

@@ -42,75 +42,50 @@ define i32 @umax(i32 %arg) { ; FAST-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> undef, <2 x i64> undef) ; FAST-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 =

[llvm-branch-commits] [CodeGen] Add dump() to MachineTraceMetrics.h (PR #97799)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/97799 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Call SimplifyDemandedBits on copysign value operand (PR #97180)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/97180 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)

RKSimon wrote: > > @AtariDreams I've noticed you've filed a lot of backport requests. How are > > you choosing which fixes to backport? Is there a specific use case you care > > about? > > There a particular LLVM miscompile bug in WebKit I'm trying to figure out. > It's been there since 2019

[llvm-branch-commits] [llvm] release/18.x: [X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125) (PR #91425)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91425 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125) (PR #91161)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91161 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86][EVEX512] Add `HasEVEX512` when `NoVLX` used for 512-bit patterns (#91106) (PR #91118)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91118 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86][EVEX512] Check hasEVEX512 for canExtendTo512DQ (#90390) (PR #90422)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90422 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/18.x [X86_64] fix SSE type error in vaarg (PR #86698)

RKSimon wrote: What are the current rules on cherry picks for old bugs? AFAICT this patch wasn't fixing a bug introduced in the 17.x-18.x development region. https://github.com/llvm/llvm-project/pull/86698 ___ llvm-branch-commits mailing list llvm-bra

[llvm-branch-commits] [llvm] release/18.x: [X86] Resolve FIXME: Enable PC relative calls on Windows (PR #84185)

RKSimon wrote: Now that 18.1 has been released - we shouldn't be merging anything that isn't just a regression from 17.x I've tried to find the release policy for this in case 18.2 is now allow further merges but I can't find anything? https://github.com/llvm/llvm-project/pull/84185 _

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Add test for aliasing miscompile fixed by #83017. NFC (PR #83856)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/83856 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Change computeAliasing signature from optional to LocationSize. (#83017) (PR #83848)

RKSimon wrote: @davemgreen Are there further patches for scalable types coming or is this just to address the ~UINT64_T(0) bugfix? https://github.com/llvm/llvm-project/pull/83848 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] Backport [DAGCombine] Fix multi-use miscompile in load combine (#81586) (PR #81633)

https://github.com/RKSimon approved this pull request. LGTM for backport https://github.com/llvm/llvm-project/pull/81633 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch

[llvm-branch-commits] [llvm] [llvm-exegesis] Add additional validation counters (PR #76788)

RKSimon wrote: Thanks, no more comments from me - but a exegesis owner should review the rest https://github.com/llvm/llvm-project/pull/76788 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman

[llvm-branch-commits] [llvm] [llvm-exegesis] Add additional validation counters (PR #76788)

@@ -121,7 +121,12 @@ def HaswellPfmCounters : ProcPfmCounters { PfmIssueCounter<"HWPort7", "uops_executed_port:port_7"> ]; let ValidationCounters = [ -PfmValidationCounter +PfmValidationCounter, +PfmValidationCounter, +PfmValidationCounter, +PfmValid

[llvm-branch-commits] [llvm] abc60e9 - [X86] vec_fabs.ll - add SSE test coverage

Author: Simon Pilgrim Date: 2023-11-30T10:07:00Z New Revision: abc60e9808820c3f6614e6815909d43ed085460e URL: https://github.com/llvm/llvm-project/commit/abc60e9808820c3f6614e6815909d43ed085460e DIFF: https://github.com/llvm/llvm-project/commit/abc60e9808820c3f6614e6815909d43ed085460e.diff LOG:

[llvm-branch-commits] [llvm] 48e1434 - [X86] Move combineToExtendBoolVectorInReg before the select combines. NFC.

Author: Simon Pilgrim Date: 2022-02-11T16:51:46Z New Revision: 48e1434a0a77852f58c1617123f228f1069ba775 URL: https://github.com/llvm/llvm-project/commit/48e1434a0a77852f58c1617123f228f1069ba775 DIFF: https://github.com/llvm/llvm-project/commit/48e1434a0a77852f58c1617123f228f1069ba775.diff LOG:

[llvm-branch-commits] [llvm] 827d0c5 - [X86] combineToExtendBoolVectorInReg - use explicit arguments. NFC.

Author: Simon Pilgrim Date: 2022-02-11T16:40:29Z New Revision: 827d0c51be93c4b0bcbe43a6cbbcc0e65a8b9f58 URL: https://github.com/llvm/llvm-project/commit/827d0c51be93c4b0bcbe43a6cbbcc0e65a8b9f58 DIFF: https://github.com/llvm/llvm-project/commit/827d0c51be93c4b0bcbe43a6cbbcc0e65a8b9f58.diff LOG:

[llvm-branch-commits] [llvm] 13f2aee - [X86][AVX] Generalize vperm2f128/vperm2i128 patterns to support all legal 256-bit vector types

Author: Simon Pilgrim Date: 2021-01-25T15:35:36Z New Revision: 13f2aee7831c9bec17006a6d401008df541a121d URL: https://github.com/llvm/llvm-project/commit/13f2aee7831c9bec17006a6d401008df541a121d DIFF: https://github.com/llvm/llvm-project/commit/13f2aee7831c9bec17006a6d401008df541a121d.diff LOG:

[llvm-branch-commits] [llvm] 821a51a - [X86][AVX] combineX86ShuffleChainWithExtract - widen to at least original root size. NFCI.

Author: Simon Pilgrim Date: 2021-01-25T13:45:37Z New Revision: 821a51a9cacfac7da8b34ccc0498d316471f1dbc URL: https://github.com/llvm/llvm-project/commit/821a51a9cacfac7da8b34ccc0498d316471f1dbc DIFF: https://github.com/llvm/llvm-project/commit/821a51a9cacfac7da8b34ccc0498d316471f1dbc.diff LOG:

[llvm-branch-commits] [llvm] 1b780cf - [X86][AVX] LowerTRUNCATE - avoid bitcasts around extract_subvectors.

Author: Simon Pilgrim Date: 2021-01-25T12:10:36Z New Revision: 1b780cf32e3eea193aa2255b852a7ef164ea00a5 URL: https://github.com/llvm/llvm-project/commit/1b780cf32e3eea193aa2255b852a7ef164ea00a5 DIFF: https://github.com/llvm/llvm-project/commit/1b780cf32e3eea193aa2255b852a7ef164ea00a5.diff LOG:

[llvm-branch-commits] [llvm] f461e35 - [X86][AVX] combineX86ShuffleChain - avoid bitcasts around insert_subvector() shuffle patterns.

Author: Simon Pilgrim Date: 2021-01-25T11:35:45Z New Revision: f461e35cbafed593e637305e2a76822dfb7ca6c7 URL: https://github.com/llvm/llvm-project/commit/f461e35cbafed593e637305e2a76822dfb7ca6c7 DIFF: https://github.com/llvm/llvm-project/commit/f461e35cbafed593e637305e2a76822dfb7ca6c7.diff LOG:

[llvm-branch-commits] [llvm] 9641bd0 - [TableGen] RuleMatcher::defineComplexSubOperand avoid std::string copy. NFCI.

Author: Simon Pilgrim Date: 2021-01-25T11:35:44Z New Revision: 9641bd0f87dda34c09c606358bb0cb08a641a4f6 URL: https://github.com/llvm/llvm-project/commit/9641bd0f87dda34c09c606358bb0cb08a641a4f6 DIFF: https://github.com/llvm/llvm-project/commit/9641bd0f87dda34c09c606358bb0cb08a641a4f6.diff LOG:

[llvm-branch-commits] [llvm] 344afa8 - [Support] TrigramIndex::insert - pass std::String argument by const reference. NFCI.

Author: Simon Pilgrim Date: 2021-01-23T11:04:00Z New Revision: 344afa853fcfcc085cb5c957b4a07c7ea013bb1b URL: https://github.com/llvm/llvm-project/commit/344afa853fcfcc085cb5c957b4a07c7ea013bb1b DIFF: https://github.com/llvm/llvm-project/commit/344afa853fcfcc085cb5c957b4a07c7ea013bb1b.diff LOG:

[llvm-branch-commits] [llvm] bd122f6 - [X86][AVX] canonicalizeLaneShuffleWithRepeatedOps - handle vperm2x128(movddup(x), movddup(y)) cases

Author: Simon Pilgrim Date: 2021-01-22T16:05:19Z New Revision: bd122f6d217862b4631ac118c58f62a7dec16a02 URL: https://github.com/llvm/llvm-project/commit/bd122f6d217862b4631ac118c58f62a7dec16a02 DIFF: https://github.com/llvm/llvm-project/commit/bd122f6d217862b4631ac118c58f62a7dec16a02.diff LOG:

[llvm-branch-commits] [llvm] c33d36e - [X86][AVX] canonicalizeLaneShuffleWithRepeatedOps - handle unary vperm2x128(permute/shift(x, c), undef) cases

Author: Simon Pilgrim Date: 2021-01-22T15:47:23Z New Revision: c33d36e0667e7fff186243ac7a3a9cd63e797438 URL: https://github.com/llvm/llvm-project/commit/c33d36e0667e7fff186243ac7a3a9cd63e797438 DIFF: https://github.com/llvm/llvm-project/commit/c33d36e0667e7fff186243ac7a3a9cd63e797438.diff LOG:

[llvm-branch-commits] [llvm] 4846f6a - [X86][AVX] combineTargetShuffle - simplify the X86ISD::VPERM2X128 subvector matching

Author: Simon Pilgrim Date: 2021-01-22T15:47:22Z New Revision: 4846f6ab815c34f6ffbc8d4ecde891d917bf2157 URL: https://github.com/llvm/llvm-project/commit/4846f6ab815c34f6ffbc8d4ecde891d917bf2157 DIFF: https://github.com/llvm/llvm-project/commit/4846f6ab815c34f6ffbc8d4ecde891d917bf2157.diff LOG:

[llvm-branch-commits] [llvm] b1166e1 - [X86][AVX] combineX86ShufflesRecursively - attempt to constant fold before widening shuffle inputs

Author: Simon Pilgrim Date: 2021-01-22T13:19:35Z New Revision: b1166e1317c54e9cfbb28b280af12313cf325a86 URL: https://github.com/llvm/llvm-project/commit/b1166e1317c54e9cfbb28b280af12313cf325a86 DIFF: https://github.com/llvm/llvm-project/commit/b1166e1317c54e9cfbb28b280af12313cf325a86.diff LOG:

[llvm-branch-commits] [llvm] 5dbe5d2 - [DAG] Commute shuffle(splat(A, u), shuffle(C, D)) -> shuffle'(shuffle(C, D), splat(A, u))

Author: Simon Pilgrim Date: 2021-01-22T11:43:18Z New Revision: 5dbe5d2c91209db9830d5b17093c408f22a7b471 URL: https://github.com/llvm/llvm-project/commit/5dbe5d2c91209db9830d5b17093c408f22a7b471 DIFF: https://github.com/llvm/llvm-project/commit/5dbe5d2c91209db9830d5b17093c408f22a7b471.diff LOG:

[llvm-branch-commits] [llvm] ffe72f9 - [X86][SSE] Don't fold shuffle(binop(), binop()) -> binop(shuffle(), shuffle()) if the shuffle are splats

Author: Simon Pilgrim Date: 2021-01-22T11:31:38Z New Revision: ffe72f987f4866c46c18174cdb750dea88bedba3 URL: https://github.com/llvm/llvm-project/commit/ffe72f987f4866c46c18174cdb750dea88bedba3 DIFF: https://github.com/llvm/llvm-project/commit/ffe72f987f4866c46c18174cdb750dea88bedba3.diff LOG:

[llvm-branch-commits] [llvm] 481659c - [X86][SSE] Add v16i8 02_20_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu shuffle test

Author: Simon Pilgrim Date: 2021-01-22T10:05:22Z New Revision: 481659c55c4ec1e133bec82a909e9e6baee70a28 URL: https://github.com/llvm/llvm-project/commit/481659c55c4ec1e133bec82a909e9e6baee70a28 DIFF: https://github.com/llvm/llvm-project/commit/481659c55c4ec1e133bec82a909e9e6baee70a28.diff LOG:

[llvm-branch-commits] [llvm] 636b877 - [X86][SSE] Add PR48823 HSUB test case

Author: Simon Pilgrim Date: 2021-01-22T10:05:22Z New Revision: 636b87785c1de64134254b688d30ab1248b16ed2 URL: https://github.com/llvm/llvm-project/commit/636b87785c1de64134254b688d30ab1248b16ed2 DIFF: https://github.com/llvm/llvm-project/commit/636b87785c1de64134254b688d30ab1248b16ed2.diff LOG:

[llvm-branch-commits] [llvm] 69bc099 - [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (REAPPLIED).

Author: Simon Pilgrim Date: 2021-01-21T13:01:34Z New Revision: 69bc0990a9181e6eb86228276d2f59435a7fae67 URL: https://github.com/llvm/llvm-project/commit/69bc0990a9181e6eb86228276d2f59435a7fae67 DIFF: https://github.com/llvm/llvm-project/commit/69bc0990a9181e6eb86228276d2f59435a7fae67.diff LOG:

[llvm-branch-commits] [llvm] 0ca81b9 - [X86][SSE] Add uitofp(trunc(and(lshr(x, c)))) vector test

Author: Simon Pilgrim Date: 2021-01-21T12:38:36Z New Revision: 0ca81b90d19d395c4891b7507cec0f063dd26d22 URL: https://github.com/llvm/llvm-project/commit/0ca81b90d19d395c4891b7507cec0f063dd26d22 DIFF: https://github.com/llvm/llvm-project/commit/0ca81b90d19d395c4891b7507cec0f063dd26d22.diff LOG:

[llvm-branch-commits] [llvm] 935bacd - [DAG] SimplifyDemandedBits - correctly adjust truncated shift amount type

Author: Simon Pilgrim Date: 2021-01-21T12:38:36Z New Revision: 935bacd3a7244f04b7f39818e3fc589529474d13 URL: https://github.com/llvm/llvm-project/commit/935bacd3a7244f04b7f39818e3fc589529474d13 DIFF: https://github.com/llvm/llvm-project/commit/935bacd3a7244f04b7f39818e3fc589529474d13.diff LOG:

[llvm-branch-commits] [llvm] bc9ab9a - [DAG] CombineToPreIndexedLoadStore - use const APInt& for getAPIntValue(). NFCI.

Author: Simon Pilgrim Date: 2021-01-21T11:04:09Z New Revision: bc9ab9a5cd6bafc5e1293f3d5d51638f8f5cd26c URL: https://github.com/llvm/llvm-project/commit/bc9ab9a5cd6bafc5e1293f3d5d51638f8f5cd26c DIFF: https://github.com/llvm/llvm-project/commit/bc9ab9a5cd6bafc5e1293f3d5d51638f8f5cd26c.diff LOG:

[llvm-branch-commits] [llvm] 86021d9 - [X86] Avoid a std::string copy by replacing auto with const auto&. NFC.

Author: Simon Pilgrim Date: 2021-01-21T11:04:07Z New Revision: 86021d98d3f8b27f7956cee04f11505c2e836e81 URL: https://github.com/llvm/llvm-project/commit/86021d98d3f8b27f7956cee04f11505c2e836e81 DIFF: https://github.com/llvm/llvm-project/commit/86021d98d3f8b27f7956cee04f11505c2e836e81.diff LOG:

[llvm-branch-commits] [llvm] b8b5e87 - [X86][AVX] Handle vperm2x128 shuffling of a subvector splat.

Author: Simon Pilgrim Date: 2021-01-20T18:16:33Z New Revision: b8b5e87e6b8102d77e4e6beccf4e0f0237acc897 URL: https://github.com/llvm/llvm-project/commit/b8b5e87e6b8102d77e4e6beccf4e0f0237acc897 DIFF: https://github.com/llvm/llvm-project/commit/b8b5e87e6b8102d77e4e6beccf4e0f0237acc897.diff LOG:

[llvm-branch-commits] [llvm] cad4275 - [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE

Author: Simon Pilgrim Date: 2021-01-20T15:39:58Z New Revision: cad4275d697c601761e0819863f487def73c67f8 URL: https://github.com/llvm/llvm-project/commit/cad4275d697c601761e0819863f487def73c67f8 DIFF: https://github.com/llvm/llvm-project/commit/cad4275d697c601761e0819863f487def73c67f8.diff LOG:

[llvm-branch-commits] [llvm] 19d0284 - [X86][AVX] Fold extract_subvector(VSRLI/VSHLI(x, 32)) -> VSRLI/VSHLI(extract_subvector(x), 32)

Author: Simon Pilgrim Date: 2021-01-20T14:34:54Z New Revision: 19d02842ee56089b9208875ce4582e113e08fb6d URL: https://github.com/llvm/llvm-project/commit/19d02842ee56089b9208875ce4582e113e08fb6d DIFF: https://github.com/llvm/llvm-project/commit/19d02842ee56089b9208875ce4582e113e08fb6d.diff LOG:

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