https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/148630
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148630?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/148630
Directly plug it into the MMO instead, which is much cleaner.
>From d8aad39519972bf64d868e9f54ac45862b92686a Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 14 Jul 2025 15:02:31 +0200
Subject: [PATCH] [NFC
https://github.com/Pierre-vh approved this pull request.
Test changes LGTM so I'm already giving this +1, though once the stack is
approved wait a day or two to see if any other reviewer has concerns about
default enabling this
https://github.com/llvm/llvm-project/pull/146076
_
https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/145329
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/143881
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
Pierre-vh wrote:
ping
https://github.com/llvm/llvm-project/pull/141589
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -669,6 +679,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-WGP-NEXT:s_wait_kmcnt 0x0
; GFX12-WGP-NEXT:s_wait_storecnt 0x0
; GFX12-WGP-NEXT:global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
+; GFX12-WGP-NEXT:s_wait_loadcnt 0x3f
@@ -669,6 +679,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-WGP-NEXT:s_wait_kmcnt 0x0
; GFX12-WGP-NEXT:s_wait_storecnt 0x0
; GFX12-WGP-NEXT:global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
+; GFX12-WGP-NEXT:s_wait_loadcnt 0x3f
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From b386d126b9f560bf203fd044d81575ddfad2a8c6 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From b386d126b9f560bf203fd044d81575ddfad2a8c6 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From d906a978145aabae8b2d1a029477d5a08272ae8c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/4] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
@@ -669,6 +679,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-WGP-NEXT:s_wait_kmcnt 0x0
; GFX12-WGP-NEXT:s_wait_storecnt 0x0
; GFX12-WGP-NEXT:global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
+; GFX12-WGP-NEXT:s_wait_loadcnt 0x3f
@@ -392,6 +394,55 @@ void
AMDGPURegBankCombinerImpl::applyCanonicalizeZextShiftAmt(
MI.eraseFromParent();
}
+bool AMDGPURegBankCombinerImpl::lowerUniformBFX(MachineInstr &MI) const {
+ assert(MI.getOpcode() == TargetOpcode::G_UBFX ||
+ MI.getOpcode() == TargetOpcod
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146055
>From c8532366fcb92ff3b3e7402118224f137e2c8980 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 27 Jun 2025 12:04:53 +0200
Subject: [PATCH] [GISel] Combine compare of bitfield extracts or'd together.
Equiva
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From d906a978145aabae8b2d1a029477d5a08272ae8c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/3] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 129c674e3c2ede4b1941b8dd40d55cbd4c23d722 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From d906a978145aabae8b2d1a029477d5a08272ae8c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/3] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 129c674e3c2ede4b1941b8dd40d55cbd4c23d722 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
Pierre-vh wrote:
> Does this also handle the case where _all_ of the values ORed together are
> shifted, like `(setcc ((x >> c0 | x >> c1 | ...) & mask))` ?
Yes, i added a test for it
https://github.com/llvm/llvm-project/pull/146054
___
llvm-branch-c
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146055
>From c8532366fcb92ff3b3e7402118224f137e2c8980 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 27 Jun 2025 12:04:53 +0200
Subject: [PATCH] [GISel] Combine compare of bitfield extracts or'd together.
Equiva
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146054
>From 26615132899d40b8d245fd98d093ef8c26cdc3e1 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:31:37 +0200
Subject: [PATCH 1/3] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences
Fold
Pierre-vh wrote:
ping
https://github.com/llvm/llvm-project/pull/141589
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/145484
>From b031681978e2b356c2ae8e65d6e08515c0044ac1 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 24 Jun 2025 11:35:58 +0200
Subject: [PATCH 1/2] [AMDGPU] Use reverse iteration in CodeGenPrepare
In order to m
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146054
>From 26615132899d40b8d245fd98d093ef8c26cdc3e1 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:31:37 +0200
Subject: [PATCH 1/2] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences
Fold
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146055
>From d97992ef24abae69878fd1e49270bf0f7372ca39 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 27 Jun 2025 12:04:53 +0200
Subject: [PATCH] [GISel] Combine compare of bitfield extracts or'd together.
Equiva
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146053
>From f137136b2f527aaf1b2f2847e821085aabfc299e Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:08:31 +0200
Subject: [PATCH 1/2] [AMDGPU] Add tests for workgroup/workitem intrinsic
optimizati
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146054
>From 26615132899d40b8d245fd98d093ef8c26cdc3e1 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:31:37 +0200
Subject: [PATCH 1/2] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences
Fold
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146053
>From f137136b2f527aaf1b2f2847e821085aabfc299e Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:08:31 +0200
Subject: [PATCH 1/2] [AMDGPU] Add tests for workgroup/workitem intrinsic
optimizati
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146055
>From d97992ef24abae69878fd1e49270bf0f7372ca39 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 27 Jun 2025 12:04:53 +0200
Subject: [PATCH] [GISel] Combine compare of bitfield extracts or'd together.
Equiva
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146054
>From 17ac90ad1ee167f35321e01625a207f2b94ff523 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:31:37 +0200
Subject: [PATCH 1/2] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences
Fold
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146055
>From da05cc2d920917f0cb6f171b0d9e2e535836ca3c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 27 Jun 2025 12:04:53 +0200
Subject: [PATCH] [GISel] Combine compare of bitfield extracts or'd together.
Equiva
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146053
>From 3f62ab3beb30abbf8c8c32dd79c0133f7ca122e0 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:08:31 +0200
Subject: [PATCH 1/2] [AMDGPU] Add tests for workgroup/workitem intrinsic
optimizati
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146054
>From 17ac90ad1ee167f35321e01625a207f2b94ff523 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:31:37 +0200
Subject: [PATCH 1/2] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences
Fold
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146055
>From da05cc2d920917f0cb6f171b0d9e2e535836ca3c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 27 Jun 2025 12:04:53 +0200
Subject: [PATCH] [GISel] Combine compare of bitfield extracts or'd together.
Equiva
@@ -28909,13 +28909,97 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern suc
@@ -28909,13 +28909,97 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern suc
Pierre-vh wrote:
> Why DAG and not InstCombine for this?
The intrinsics we want to optimize with this aren't lowered yet at IC
https://github.com/llvm/llvm-project/pull/146054
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
htt
@@ -188,7 +188,11 @@ enum RegBankLLTMappingApplyID {
Sgpr32Trunc,
- // Src only modifiers: waterfalls, extends
+ // Src only modifiers: execute in waterfall loop if divergent
+ Sgpr32_W,
Pierre-vh wrote:
nit: use a suffix like `_WF` for WaterFall?
I kee
@@ -57,6 +57,224 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
https://github.com/Pierre-vh edited
https://github.com/llvm/llvm-project/pull/146054
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/146055
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/146053
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/146054
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146054?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146055?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146053?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/146055
Equivalent of the previous DAG patch for GISel.
The shifts are BFXs in GISel, so the canonical form of the entire expression
is different than in the DAG. The mask is not at the root of the expression, it
remai
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/146053
None
>From 3f62ab3beb30abbf8c8c32dd79c0133f7ca122e0 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:08:31 +0200
Subject: [PATCH] [AMDGPU] Add tests for workgroup/workitem intrinsic
optimiza
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/146054
Fold sequences where we extract a bunch of contiguous bits from a value,
merge them into the low bit and then check if the low bits are zero or not.
It seems like a strange sequence at first but it's an idiom
@@ -109,6 +110,7 @@ class AMDGPUCodeGenPrepareImpl
bool FlowChanged = false;
mutable Function *SqrtF32 = nullptr;
mutable Function *LdexpF32 = nullptr;
+ mutable SetVector DeadVals;
Pierre-vh wrote:
I didn't use a set because I thought we could visit tw
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 642055d06b93df98e4f57c226d170f236014077c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 642055d06b93df98e4f57c226d170f236014077c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 6773e3b993fa25fa1087eae3db26d0244be6309b Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 6773e3b993fa25fa1087eae3db26d0244be6309b Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/145484
In order to make this easier, I also removed all "removeFromParent" calls from
the visitors, instead adding instructions
to a set of instructions to delete once the function has been visited.
This avoids crash
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145484?utm_source=stack-comment-downstack-mergeability-warning
@@ -2160,7 +2160,22 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr
addrspace(1) %out, <2 x flo
; IEEE-GOODFREXP-NEXT:[[TMP38:%.*]] = insertelement <2 x float> poison,
float [[TMP27]], i64 0
; IEEE-GOODFREXP-NEXT:[[MD_1ULP_UNDEF:%.*]] = insertelement <2 x float
@@ -1634,29 +1634,18 @@ define float @v_recip_sqrt_f32_ulp25_contract(float %x)
{
; IR-IEEE-SDAG-LABEL: v_recip_sqrt_f32_ulp25_contract:
; IR-IEEE-SDAG: ; %bb.0:
; IR-IEEE-SDAG-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; IR-IEEE-SDAG-NEXT:s_mov_b32 s4, 0xf800
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/145484
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 10a9e08e314dcb5a57fd1c6a6e818a4146ed9210 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 76be3031e6f1195263d63fd09d2f0087a7f5e853 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 10a9e08e314dcb5a57fd1c6a6e818a4146ed9210 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 76be3031e6f1195263d63fd09d2f0087a7f5e853 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
@@ -203,7 +205,14 @@ class AMDGPURegBankLegalizeCombiner {
bool tryEliminateReadAnyLane(MachineInstr &Copy) {
Register Dst = Copy.getOperand(0).getReg();
Register Src = Copy.getOperand(1).getReg();
-if (!Src.isVirtual())
+
+// Skip non-vgpr Dst
+if ((Dst.i
@@ -137,7 +138,109 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::pair tryMatchRALFromUnmerge(Register Src) {
+MachineInstr *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGP
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/142789
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
Pierre-vh wrote:
### Merge activity
* **Jun 19, 7:48 AM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/142601).
https://github.com/llvm/llvm-project/pull/142601
__
Pierre-vh wrote:
### Merge activity
* **Jun 19, 7:48 AM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/142604).
https://github.com/llvm/llvm-project/pull/142604
__
Pierre-vh wrote:
### Merge activity
* **Jun 19, 7:48 AM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/142602).
https://github.com/llvm/llvm-project/pull/142602
__
Pierre-vh wrote:
### Merge activity
* **Jun 19, 7:48 AM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/142603).
https://github.com/llvm/llvm-project/pull/142603
__
Pierre-vh wrote:
ping
https://github.com/llvm/llvm-project/pull/141590
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
Pierre-vh wrote:
@petar-avramovic If this is good, can you approve it so I can land it once all
other patches are approved? Thanks :)
https://github.com/llvm/llvm-project/pull/142602
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.
Pierre-vh wrote:
ping
https://github.com/llvm/llvm-project/pull/142601
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
@@ -894,6 +1121,15 @@ void RegBankLegalizeHelper::applyMappingSrc(
}
break;
}
+// sgpr waterfall, scalars and vectors
+case Sgpr32_W:
+case SgprV4S32_W: {
+ assert(Ty == getTyFromID(MethodIDs[i]));
+ if (RB != SgprRB) {
+SgprWaterfa
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
@@ -165,6 +165,8 @@ enum RegBankLLTMappingApplyID {
Sgpr32Trunc,
// Src only modifiers: waterfalls, extends
+ Sgpr32_W,
+ SgprV4S32_W,
Pierre-vh wrote:
Can you add a trailing comment or rename this ? The `_W` suffix is not
immediately clear to me
http
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect
-regbankselect-fast -o - %s | FileCheck %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-afte
@@ -117,45 +117,73 @@ static LLT getReadAnyLaneSplitTy(LLT Ty) {
return LLT::scalar(32);
}
-static Register buildReadAnyLane(MachineIRBuilder &B, Register VgprSrc,
- const RegisterBankInfo &RBI);
+typedef std::functionhttps://github.com/llvm/l
@@ -117,45 +117,73 @@ static LLT getReadAnyLaneSplitTy(LLT Ty) {
return LLT::scalar(32);
}
-static Register buildReadAnyLane(MachineIRBuilder &B, Register VgprSrc,
- const RegisterBankInfo &RBI);
+typedef std::function
+ReadLaneFnTy;
+
+st
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
Pierre-vh wrote:
```suggestion
std::pair tryMatchRALFromUnmerge(Register Src) {
```
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
Pierre-vh wrote:
```suggestion
Machin
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/142604
>From 9fd34f632f194a025669b2c2c0f83d19fb48b00c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 15:08:06 +0200
Subject: [PATCH 1/3] [AMDGPU] New RegBankSelect: Add rules for `G_PTRTOINT`
and `G_I
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/142601
>From 96669eee5e756faed679480521faafd9f1bad9d1 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 13:27:55 +0200
Subject: [PATCH] [AMDGPU] New RegBanKSelect: Add S128 types
---
llvm/lib/Target/AMD
https://github.com/Pierre-vh closed
https://github.com/llvm/llvm-project/pull/142600
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/Pierre-vh edited
https://github.com/llvm/llvm-project/pull/142601
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/142602
>From c69258d78459b8dcc89bec38a8a795763cd3dc80 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 14:40:38 +0200
Subject: [PATCH] [AMDGPU] New RegBankSelect: Add Ptr32/Ptr64/Ptr128
There's quite a
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/142602
>From c69258d78459b8dcc89bec38a8a795763cd3dc80 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 14:40:38 +0200
Subject: [PATCH] [AMDGPU] New RegBankSelect: Add Ptr32/Ptr64/Ptr128
There's quite a
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/142603
>From 3a47927dfaaa98cb0d2a336bfa416d2eb28e294d Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 15:03:01 +0200
Subject: [PATCH] [AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT
Test P
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/142603
>From 3a47927dfaaa98cb0d2a336bfa416d2eb28e294d Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 15:03:01 +0200
Subject: [PATCH] [AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT
Test P
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/142601
>From 96669eee5e756faed679480521faafd9f1bad9d1 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 13:27:55 +0200
Subject: [PATCH] [AMDGPU] New RegBanKSelect: Add S128 types
---
llvm/lib/Target/AMD
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/142604
>From 9fd34f632f194a025669b2c2c0f83d19fb48b00c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 15:08:06 +0200
Subject: [PATCH 1/3] [AMDGPU] New RegBankSelect: Add rules for `G_PTRTOINT`
and `G_I
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/142604
>From f9141055a09fc376354f901932b0a39e28d58c35 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 15:08:06 +0200
Subject: [PATCH 1/2] [AMDGPU] New RegBankSelect: Add rules for `G_PTRTOINT`
and `G_I
1 - 100 of 281 matches
Mail list logo
