[llvm-branch-commits] [clang] [llvm] [X86] Backport new intrinsic and instruction changes in AVX10.2 (PR #133219)

2025-04-13 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > > > Doesn't this break ABI by changing intrinsic / builtin numbers? > > > > > > So the headers could still be updated but must use the existing builtins in > > the backport? > > Sounds good, I can try with it. Thanks! A reduced one for intrinsics only https://github.com/

[llvm-branch-commits] [clang] [llvm] [X86] Backport new intrinsic and instruction changes in AVX10.2 (PR #133219)

2025-04-13 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang closed https://github.com/llvm/llvm-project/pull/133219 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [X86] Backport new intrinsic and instruction changes in AVX10.2 (PR #133219)

2025-04-09 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > > Doesn't this break ABI by changing intrinsic / builtin numbers? > > So the headers could still be updated but must use the existing builtins in > the backport? Sounds good, I can try with it. Thanks! https://github.com/llvm/llvm-project/pull/133219 __

[llvm-branch-commits] [llvm] release/20.x: [X86] When expanding LCMPXCHG16B_SAVE_RBX, substitute RBX in base (#134109) (PR #134331)

2025-04-05 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang approved this pull request. https://github.com/llvm/llvm-project/pull/134331 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [X86] When expanding LCMPXCHG16B_SAVE_RBX, substitute RBX in base (#134109) (PR #134331)

2025-04-04 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > @phoebewang What do you think about merging this PR to the release branch? I think it's ok to merge. https://github.com/llvm/llvm-project/pull/134331 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://l

[llvm-branch-commits] [clang] [llvm] [X86] Backport new intrinsic and instruction changes in AVX10.2 (PR #133219)

2025-03-27 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > Although these instructions aren't supported by current hardware this > probably needs a release notes entry - wdyt? Sure, added in the description. Thanks for the reminder! https://github.com/llvm/llvm-project/pull/133219 ___ llv

[llvm-branch-commits] [clang] [llvm] [X86] Backport new intrinsic and instruction changes in AVX10.2 (PR #133219)

2025-03-27 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang edited https://github.com/llvm/llvm-project/pull/133219 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/20.x: [AVX10.2] Fix wrong intrinsic names after rename (#126390) (PR #126687)

2025-02-10 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: This is a bug fix without risk, LGTM. https://github.com/llvm/llvm-project/pull/126687 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (#124511) (PR #125057)

2025-02-04 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: @e-kud Please help review it. > It had the 'needs review' status and I missed it. We can get it into -rc2. Oh, I thought it notified reviewer automaticly. Maybe because it's manully cherry-pick. https://github.com/llvm/llvm-project/pull/125057 ___

[llvm-branch-commits] [clang] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (#124511) (PR #125057)

2025-02-02 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: Ping @tstellar, any reason this was missing in rc1 release? https://github.com/llvm/llvm-project/pull/125057 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-

[llvm-branch-commits] [clang] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (#124511) (PR #125057)

2025-02-02 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/125057 >From f816bd39f6986825e338198fce8747939ab1c882 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Thu, 30 Jan 2025 21:13:49 +0800 Subject: [PATCH] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to

[llvm-branch-commits] [clang] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (#124511) (PR #125057)

2025-02-01 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/125057 >From f816bd39f6986825e338198fce8747939ab1c882 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Thu, 30 Jan 2025 21:13:49 +0800 Subject: [PATCH] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to

[llvm-branch-commits] [clang] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (#124511) (PR #125057)

2025-01-30 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang milestoned https://github.com/llvm/llvm-project/pull/125057 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (#124511) (PR #125057)

2025-01-30 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/125057 Per the feedback we got, we’d like to switch m[no-]avx10.2 to alias of 512 bit options and disable m[no-]avx10.1 due to they were alias of 256 bit options. We also change -mno-avx10.[1,2]-512 to alias of 256

[llvm-branch-commits] [llvm] release/19.x: [x86] combineMUL - when looking for a vector multiply by splat constant, ensure we're only accepting ConstantInt splat scalars. (PR #111246)

2024-10-11 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: LGTM. https://github.com/llvm/llvm-project/pull/111246 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [X86][APX] Fix wrong encoding of promoted KMOV instructions due to missing NoCD8 (#109759) (PR #109767)

2024-10-01 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: Thanks @tru! The title should be good as the description. https://github.com/llvm/llvm-project/pull/109767 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-br

[llvm-branch-commits] [llvm] release/19.x: [X86][APX] Fix wrong encoding of promoted KMOV instructions due to missing NoCD8 (#109759) (PR #109767)

2024-09-24 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang edited https://github.com/llvm/llvm-project/pull/109767 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [X86][APX] Fix wrong encoding of promoted KMOV instructions due to missing NoCD8 (#109579) (PR #109635)

2024-09-24 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang closed https://github.com/llvm/llvm-project/pull/109635 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [X86][APX] Fix wrong encoding of promoted KMOV instructions due to missing NoCD8 (#109579) (PR #109635)

2024-09-24 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: Sorry, there was a mistake with the patch. I'll close it and create another one. https://github.com/llvm/llvm-project/pull/109635 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/m

[llvm-branch-commits] [llvm] [X86][APX] Fix wrong encoding of promoted KMOV instructions due to missing NoCD8 (#109579) (PR #109635)

2024-09-23 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang milestoned https://github.com/llvm/llvm-project/pull/109635 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [X86][APX] Fix wrong encoding of promoted KMOV instructions due to missing NoCD8 (#109579) (PR #109635)

2024-09-23 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/109635 Promoted KMOV* was encoded with CD8 incorrectly, see https://godbolt.org/z/cax513hG1 >From b403d2a05b548f24b46bab4c4ae014c9949f3c44 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 23 Sep 2024 09:41:43

[llvm-branch-commits] [llvm] [X86] Avoid generating nested CALLSEQ for TLS pointer function arguments (PR #106965)

2024-09-03 Thread Phoebe Wang via llvm-branch-commits
@@ -0,0 +1,17 @@ +; RUN: llc -verify-machineinstrs < %s -relocation-model=pic + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" phoebewang wrote: Yes, we need to check the

[llvm-branch-commits] [llvm] [X86] Avoid generating nested CALLSEQ for TLS pointer function arguments (PR #106965)

2024-09-02 Thread Phoebe Wang via llvm-branch-commits
@@ -0,0 +1,17 @@ +; RUN: llc -verify-machineinstrs < %s -relocation-model=pic + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" phoebewang wrote: Do not need this. https://github.com/llvm/llvm-project/pull/106965 __

[llvm-branch-commits] [llvm] [X86] Avoid generating nested CALLSEQ for TLS pointer function arguments (PR #106965)

2024-09-02 Thread Phoebe Wang via llvm-branch-commits
@@ -0,0 +1,17 @@ +; RUN: llc -verify-machineinstrs < %s -relocation-model=pic + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; Passing a pointer to thread-local storage to a function c

[llvm-branch-commits] [llvm] [X86] Avoid generating nested CALLSEQ for TLS pointer function arguments (PR #106965)

2024-09-02 Thread Phoebe Wang via llvm-branch-commits
@@ -0,0 +1,17 @@ +; RUN: llc -verify-machineinstrs < %s -relocation-model=pic + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" phoebewang wrote: This can put in the RUN li

[llvm-branch-commits] [llvm] release/19.x: [MCA][X86] Add missing 512-bit vpscatterqd/vscatterqps schedule data (REAPPLIED) (PR #105815)

2024-08-23 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/105815 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/19.x: [X86] Use correct fp immediate types in _mm_set_ss/sd (PR #105638)

2024-08-22 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang approved this pull request. LGTM, thanks! https://github.com/llvm/llvm-project/pull/105638 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch

[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)

2024-05-13 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: This patch fixes build failures when compiling AVX512 code using `-march=native` on machines without AVX512. The problem was introduced by https://github.com/llvm/llvm-project/commit/a7b8b890600a33e0c88d639f311f1d73ccb1c8d2 which is included in LLVM 18.1.5 release. https://g

[llvm-branch-commits] [llvm] release/18.x: [X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125) (PR #91425)

2024-05-09 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > @phoebewang (or anyone else). If you would like to add a note about this fix > in the release notes (completely optional). Please reply to this comment with > a one or two sentence description of the fix. When you are done, please add > the release:note label to this PR. T

[llvm-branch-commits] [llvm] release/18.x: [X86][EVEX512] Add `HasEVEX512` when `NoVLX` used for 512-bit patterns (#91106) (PR #91118)

2024-05-09 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > @phoebewang (or anyone else). If you would like to add a note about this fix > in the release notes (completely optional). Please reply to this comment with > a one or two sentence description of the fix. When you are done, please add > the release:note label to this PR. T

[llvm-branch-commits] [llvm] release/18.x: [X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125) (PR #91161)

2024-05-07 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: The test failures are caused by LLVM 18 branch difference, created #91425 instead. https://github.com/llvm/llvm-project/pull/91161 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin

[llvm-branch-commits] [llvm] release/18.x: [X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125) (PR #91161)

2024-05-07 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang closed https://github.com/llvm/llvm-project/pull/91161 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125) (PR #91425)

2024-05-07 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang milestoned https://github.com/llvm/llvm-project/pull/91425 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125) (PR #91425)

2024-05-07 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/91425 None >From 5f3651376c051c1fb7b29741778a4616811a1157 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 6 May 2024 10:59:44 +0800 Subject: [PATCH 1/2] [X86][FP16] Do not create VBROADCAST_LOAD for f16 witho

[llvm-branch-commits] [llvm] release/18.x: [X86][EVEX512] Check hasEVEX512 for canExtendTo512DQ (#90390) (PR #90422)

2024-05-02 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > Hi @phoebewang (or anyone else). If you would like to add a note about this > fix in the release notes (completely optional). Please reply to this comment > with a one or two sentence description of the fix. When you are done, please > add the release:note label to this PR.

[llvm-branch-commits] [clang] release/18.x [X86_64] fix SSE type error in vaarg (PR #86698)

2024-04-16 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > @phoebewang What do you think about backporting this? I think the patch doesn't fix all problem in #86371, suggest to reevaluate it. @efriedma-quic may take another look. https://github.com/llvm/llvm-project/pull/86698 ___ llvm-br

[llvm-branch-commits] [llvm] release/18.x: [X86] Fix miscompile in combineShiftRightArithmetic (PR #86728)

2024-04-16 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > @phoebewang What do you think about backporting this? I didn't review on it. Maybe @topperc can evaluate it. https://github.com/llvm/llvm-project/pull/86728 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org ht

[llvm-branch-commits] [llvm] release/18.x: [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) (PR #88388)

2024-04-11 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/88388 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83834)

2024-03-12 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83834 >From 9cec3b7b1ea0491df688555a51750efe6c9bd075 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 4 Mar 2024 18:09:41 +0800 Subject: [PATCH] [X86] Add missing subvector_subreg_lowering for BF16 (#83720) --

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83834)

2024-03-12 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83834 >From 6d03789303fe3d5c84406df29353ddf63199eb08 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 4 Mar 2024 18:09:41 +0800 Subject: [PATCH] [X86] Add missing subvector_subreg_lowering for BF16 (#83720) --

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

2024-03-11 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: Please review this patch instead https://github.com/llvm/llvm-project/pull/83834 https://github.com/llvm/llvm-project/pull/84491 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/ma

[llvm-branch-commits] [llvm] [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83834)

2024-03-11 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83834 >From 6d03789303fe3d5c84406df29353ddf63199eb08 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 4 Mar 2024 18:09:41 +0800 Subject: [PATCH] [X86] Add missing subvector_subreg_lowering for BF16 (#83720) --

[llvm-branch-commits] [llvm] release/18.x: [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes (PR #84698)

2024-03-11 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: LGTM. https://github.com/llvm/llvm-project/pull/84698 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86]: Add FPCW as a rounding control register (PR #84058)

2024-03-06 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: I don't think it worth backport. The x87 usage is not very common nowadays, and the problem is lasting for a while. I'd suggest not do the backport considering it may have sideeffect in the isCall change. https://github.com/llvm/llvm-project/pull/84058 ___

[llvm-branch-commits] [llvm] release/18.x: [X86][Inline] Skip inline asm in inlining target feature check (#83820) (PR #84029)

2024-03-06 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: Risk is minimum, LGTM. https://github.com/llvm/llvm-project/pull/84029 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83834)

2024-03-04 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang milestoned https://github.com/llvm/llvm-project/pull/83834 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83834)

2024-03-04 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/83834 None >From 6d03789303fe3d5c84406df29353ddf63199eb08 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 4 Mar 2024 18:09:41 +0800 Subject: [PATCH] [X86] Add missing subvector_subreg_lowering for BF16 (#8372

[llvm-branch-commits] [llvm] [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83811)

2024-03-04 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/83811 None >From 7210a98061d9f6382e8ce4ca7646ec4a5c3f96e6 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 4 Mar 2024 17:28:23 +0800 Subject: [PATCH] [X86] Add missing subvector_subreg_lowering for BF16 (#8372

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83758)

2024-03-04 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: Some change related on trunk code, I'll create a manual cherry-pick. https://github.com/llvm/llvm-project/pull/83758 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listin

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #83758)

2024-03-04 Thread Phoebe Wang via llvm-branch-commits
https://github.com/phoebewang closed https://github.com/llvm/llvm-project/pull/83758 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#79675 (PR #79721)

2024-01-27 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > @phoebewang What do you think about merging this PR to the release branch? This patch fixes prior mistakes, so should be merged to release branch. @KanRobert Do I understand it right? https://github.com/llvm/llvm-project/pull/79721 __

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#79279 (PR #79341)

2024-01-24 Thread Phoebe Wang via llvm-branch-commits
phoebewang wrote: > @phoebewang What do you think about merging this PR to the release branch? The fix is required and has low risk, LGTM. https://github.com/llvm/llvm-project/pull/79341 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.l

[llvm-branch-commits] [clang] 5237193 - [NFC] Fix typos in comments

2023-11-29 Thread Phoebe Wang via llvm-branch-commits
Author: Phoebe Wang Date: 2023-11-19T10:14:34+08:00 New Revision: 5237193b87721134541f228e28edfd544a9c8ac8 URL: https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8 DIFF: https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8.diff L

[llvm-branch-commits] [llvm] e4b3fad - [clang][llvm][doc] Add more information for the ABI change in FP16

2022-08-04 Thread Phoebe Wang via llvm-branch-commits
Author: Phoebe Wang Date: 2022-08-04T22:31:16+08:00 New Revision: e4b3fad1facdb3f005ec77f607a2b05e3e9fcbad URL: https://github.com/llvm/llvm-project/commit/e4b3fad1facdb3f005ec77f607a2b05e3e9fcbad DIFF: https://github.com/llvm/llvm-project/commit/e4b3fad1facdb3f005ec77f607a2b05e3e9fcbad.diff L

[llvm-branch-commits] [llvm] e7b1dc9 - [X86][NFC] Pre-commit test to show prolog insert problem

2021-11-12 Thread Phoebe Wang via llvm-branch-commits
Author: Phoebe Wang Date: 2021-11-13T11:30:09+08:00 New Revision: e7b1dc9a9dbabf0a13a76d44b179c0230222 URL: https://github.com/llvm/llvm-project/commit/e7b1dc9a9dbabf0a13a76d44b179c0230222 DIFF: https://github.com/llvm/llvm-project/commit/e7b1dc9a9dbabf0a13a76d44b179c0230222.diff L

[llvm-branch-commits] [llvm] a566a4b - [X86][VARARG] Assign MMO earlier to avoid prolog insert point been sunk across VASTART_SAVE_XMM_REGS

2021-11-12 Thread Phoebe Wang via llvm-branch-commits
Author: Phoebe Wang Date: 2021-11-13T11:32:57+08:00 New Revision: a566a4b21157e7aedb6d4230f61e09f6cd3152ce URL: https://github.com/llvm/llvm-project/commit/a566a4b21157e7aedb6d4230f61e09f6cd3152ce DIFF: https://github.com/llvm/llvm-project/commit/a566a4b21157e7aedb6d4230f61e09f6cd3152ce.diff L