[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH 1/5] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/li

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH 1/5] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/li

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH 1/4] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/li

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH 1/3] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/li

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH 1/3] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/li

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH 1/3] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/li

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { } if (IsZeroCmp && ST->hasVInstructions()) { -unsigned RealMinVLen = ST->getRealMinVLen(); -// Support Fractional LMULs if the lengths are larger than XLen. -// T

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { } if (IsZeroCmp && ST->hasVInstructions()) { -unsigned RealMinVLen = ST->getRealMinVLen(); -// Support Fractional LMULs if the lengths are larger than XLen. -// T

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH 1/2] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/li

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { } if (IsZeroCmp && ST->hasVInstructions()) { -unsigned RealMinVLen = ST->getRealMinVLen(); -// Support Fractional LMULs if the lengths are larger than XLen. -// T

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { } if (IsZeroCmp && ST->hasVInstructions()) { -unsigned RealMinVLen = ST->getRealMinVLen(); -// Support Fractional LMULs if the lengths are larger than XLen. -// T

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

wangpc-pp wrote: Oh, I forgot that. Can you please test the performance impact on BPI-F3? @lukel97 https://github.com/llvm/llvm-project/pull/114971 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/lib/Ta

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/lib/Ta

[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/114517 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

@@ -16190,13 +16186,20 @@ combineVectorSizedSetCCEquality(EVT VT, SDValue X, SDValue Y, ISD::CondCode CC, return SDValue(); unsigned VecSize = OpSize / 8; - EVT VecVT = MVT::getVectorVT(MVT::i8, VecSize); - EVT CmpVT = MVT::getVectorVT(MVT::i1, VecSize); + EVT VecVT

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/lib/Ta

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/lib/Ta

[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -2952,5 +2952,22 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { Options.LoadSizes = {4, 2, 1}; Options.AllowedTailExpansions = {3}; } + + if (IsZeroCmp && ST->hasVInstructions() && ST->enableUnalignedVectorMem()) { w

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/lib/Ta

[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14520,17 +14520,78 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Try to map an integer comparison with size > XLEN to vector instructions +/// before type legalization splits it up into chunks. +static SDValue +c

[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/114517 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -2512,9 +2512,11 @@ bool RISCVTTIImpl::isProfitableToSinkOperands( RISCVTTIImpl::TTI::MemCmpExpansionOptions RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { TTI::MemCmpExpansionOptions Options; + // Here we assume that a core that has implemented

[llvm-branch-commits] [clang] [llvm] release/20.x: [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (#136842) (PR #137490)

wangpc-pp wrote: Thanks @tstellar! Now all checks are passed! https://github.com/llvm/llvm-project/pull/137490 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] release/20.x: [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (#136842) (PR #137490)

wangpc-pp wrote: > This has some failing tests. The failure is not related to this PR I think, it is about `compiler-rt/XRay`: ``` /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-6vh59-1/llvm-project/github-pull-requests/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp:57:15: error:

[llvm-branch-commits] [RISCV][NFC] Use bitmasks generated by TableGen (PR #135600)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/135600 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV][NFC] Use bitmasks generated by TableGen (PR #135600)

wangpc-pp wrote: > Is `users/wangpc-pp/spr/main.riscvnfc-use-bitmasks-generated-by-tablegen` the > correct base branch? Oh I forgot to say that this PR is stacked on #135599. https://github.com/llvm/llvm-project/pull/135600 ___ llvm-branch-commits m

[llvm-branch-commits] [RISCV][NFC] Use bitmasks generated by TableGen (PR #135600)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/135600 So that we don't need to sync-up the table manually. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman

[llvm-branch-commits] [llvm] release/20.x: [RISCV] [MachineOutliner] Analyze all candidates (#127659) (PR #128146)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/128146 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] PeepholeOpt: Fix looking for def of current copy to coalesce (PR #125533)

@@ -354,44 +353,38 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV32-NEXT:vmerge.vvm v20, v8, v16, v0 ; RV32-NEXT:addi a1, sp, 16 ; RV32-NEXT:vs4r.v v20, (a1) # Unknown-size Folded Spill -; RV32-NEXT:vmv1r.v v0, v3 +; RV

[llvm-branch-commits] [llvm] PeepholeOpt: Fix looking for def of current copy to coalesce (PR #125533)

@@ -403,236 +396,253 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV32-NEXT:add a1, sp, a1 ; RV32-NEXT:addi a1, a1, 16 ; RV32-NEXT:vs8r.v v24, (a1) # Unknown-size Folded Spill -; RV32-NEXT:vmv1r.v v0, v1 +; RV32-NEXT:

[llvm-branch-commits] [llvm] PeepholeOpt: Fix looking for def of current copy to coalesce (PR #125533)

@@ -1891,31 +1886,44 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; RV32-NEXT:addi a0, a0, 48 ; RV32-NEXT:vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT:vand.vv v16, v24, v16, v0.t -; RV32-NEXT:vsub.vv v24, v8,

[llvm-branch-commits] [llvm] [TRI] Remove reserved registers in getRegPressureSetLimit (PR #118787)

@@ -16,6 +16,6 @@ body: | $f1 = COPY %2 BLR8 implicit $lr8, implicit undef $rm, implicit $x3, implicit $f1 ... -# CHECK-DAG: AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31 $

[llvm-branch-commits] [llvm] [TRI] Remove reserved registers in getRegPressureSetLimit (PR #118787)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/118787 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [TRI] Remove reserved registers in getRegPressureSetLimit (PR #118787)

wangpc-pp wrote: > > Do you know what caused the X86 changes? I don't see any uses of > > getRegPressureSetLimit in the X86 directory. > > Just checked line by line, I have no idea why X86 has some changes... The reason may be mentally absorbing (and costed me a lot of time on debugging...):

[llvm-branch-commits] [llvm] [TRI] Remove reserved registers in getRegPressureSetLimit (PR #118787)

@@ -925,9 +925,16 @@ class TargetRegisterInfo : public MCRegisterInfo { virtual const char *getRegPressureSetName(unsigned Idx) const = 0; /// Get the register unit pressure limit for this dimension. - /// This limit must be adjusted dynamically for reserved registers. +

[llvm-branch-commits] [llvm] [TRI] Remove reserved registers in getRegPressureSetLimit (PR #118787)

wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/118787 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159) (PR #121175)

https://github.com/wangpc-pp approved this pull request. LGTM. This fixes an existing bug reported by user. https://github.com/llvm/llvm-project/pull/121175 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/

[llvm-branch-commits] [llvm] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)

wangpc-pp wrote: closed as it has been splitted into several small patches. https://github.com/llvm/llvm-project/pull/119194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-br

[llvm-branch-commits] [llvm] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/119194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/119194 >From b0d87f2a2e0ab0a13bdd85d5406451534e79ba8d Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Mon, 9 Dec 2024 19:18:06 +0800 Subject: [PATCH] Rewrite uses in AM/PPC targets Created using spr 1.3.6-beta.1

[llvm-branch-commits] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)

wangpc-pp wrote: > Why do we need #118787 if we can just update the passes to use > RegisterClassInfo? Because the APIs are messy and confusing, we don't know if there will be some future users that use the raw limit directly. https://github.com/llvm/llvm-project/pull/119194 _

[llvm-branch-commits] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/119194 To reduce compile time. This is a follow-up of #118787. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mai

[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/115843 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/115843 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/115843 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/115843 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Add TuneDisableLatencySchedHeuristic (PR #115858)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Add FeatureDisableLatencySchedHeuristic (PR #115858)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

wangpc-pp wrote: Thanks for evaluating this! The data is very helpful! @michaelmaitland > Given @michaelmaitland's data, @wangpc-pp the burden shifts to you to clearly > justify which cases this is profitable and figure out how to selectively > enable only in profitable cases. I agree with @m

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

@@ -58,6 +58,19 @@ bool hasFastVectorUnalignedAccess(StringRef CPU) { return Info && Info->FastVectorUnalignedAccess; } +bool hasValidCPUModel(StringRef CPU) { + const CPUModel CPUModel = getCPUModel(CPU); + return CPUModel.MVendorID != 0 && CPUModel.MArchID != 0 && --

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] mimplid->mimpid (PR #116745)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/116745 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] mimplid->mimpid (PR #116745)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/116745 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

@@ -22505,6 +22506,47 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID, return nullptr; } +Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) { + const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts(); + StringRef CPUStr = cast(CPUExpr)->getStri

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/115843 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/115843 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/116231 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

@@ -22505,6 +22506,57 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID, return nullptr; } +Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) { + const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts(); + StringRef CPUStr = cast(CPUExpr)->getStri

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/2] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/3] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH] Remove stale CHECKs Created using spr 1.3.6-beta.1 --- clan

[llvm-branch-commits] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/116231 We have defined `__riscv_cpu_model` variable in #101449. It contains `mvendorid`, `marchid` and `mimpid` fields which are read via system call `sys_riscv_hwprobe`. We can support `__builtin_cpu_is` via compari

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

wangpc-pp wrote: I added two experimental options: `-riscv-disable-latency-heuristic` and `-riscv-should-track-lane-masks` and evaluated the statistics (`regalloc.NumSpills`/`regalloc.NumReloads`) on llvm-test-suite (option: `-O3 -march=rva23u64`): 1. `-riscv-disable-latency-heuristic=true` an

[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

wangpc-pp wrote: Paste the data here as well I added two experimental options: `-riscv-disable-latency-heuristic` and `-riscv-should-track-lane-masks` and evaluated the statistics (`regalloc.NumSpills`/`regalloc.NumReloads`) on llvm-test-suite (option: `-O3 -march=rva23u64`): 1. `-riscv

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/115858 This helps reduce register pressure for some cases. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/

[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

@@ -23,11 +23,12 @@ define <8 x i32> @concat_2xv4i32(<4 x i32> %a, <4 x i32> %b) { define <8 x i32> @concat_4xv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) { ; VLA-LABEL: concat_4xv2i32: ; VLA: # %bb.0: +; VLA-NEXT:vmv1r.v v12, v10 w

[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/115843 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/115843 This can help to improve the register pressure for LMUL>1 cases. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi

[llvm-branch-commits] [RISCV] Add vcpop.m/vfirst.m to RISCVMaskedPseudosTable (PR #115162)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/115162 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Add vcpop.m/vfirst.m to RISCVMaskedPseudosTable (PR #115162)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/115162 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind optsize { ; ; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15: ; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry -; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0) -; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind optsize { ; ; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15: ; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry -; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0) -; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind optsize { ; ; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15: ; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry -; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0) -; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/lib/Ta

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/lib/Ta

[llvm-branch-commits] [RISCV] Add vcpop.m/vfirst.m to RISCVMaskedPseudosTable (PR #115162)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/115162 We seem to forget these two instructions. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/l

[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -2525,5 +2527,21 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { Options.LoadSizes = {8, 4, 2, 1}; else Options.LoadSizes = {4, 2, 1}; + if (IsZeroCmp && ST->hasVInstructions()) { wangpc-pp wrote: Good catch! I will

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/lib/Ta

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/114971 >From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 5 Nov 2024 20:38:44 +0800 Subject: [PATCH] Set max bytes Created using spr 1.3.6-beta.1 --- llvm/lib/Ta

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

wangpc-pp wrote: > > > > Can we break the enabling down into more manageable pieces? I think > > > > `enableUnalignedScalarMem() && (Subtarget->hasStdExtZbb() || > > > > Subtarget->hasStdExtZbkb() || IsZeroCmp)` might be a good starting > > > > point. > > > > > > > > > I'd be fine with this

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