[llvm-branch-commits] [llvm] [AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (PR #130041)

2025-04-05 Thread Mirko Brkušanin via llvm-branch-commits
@@ -1509,18 +1509,18 @@ multiclass MIMG_Gather : MIMG_Gather; -class MIMG_IntersectRay_Helper { - int num_addrs = !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 11)); +class MIMG_IntersectRay_Helper { + int num_addrs = !if(isBVH8, 11, !if(Is64, !if(IsA16, 9, 12), !if(IsA16,

[llvm-branch-commits] [llvm] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (PR #130094)

2025-03-14 Thread Mirko Brkušanin via llvm-branch-commits
@@ -1200,34 +1225,79 @@ bool AMDGPUCallLowering::lowerTailCall( if (!IsSibCall) CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP); - unsigned Opc = - getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC); + bool IsChainCall = AMDGPU::isC

[llvm-branch-commits] [llvm] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (PR #130094)

2025-03-14 Thread Mirko Brkušanin via llvm-branch-commits
@@ -1200,34 +1225,79 @@ bool AMDGPUCallLowering::lowerTailCall( if (!IsSibCall) CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP); - unsigned Opc = - getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC); + bool IsChainCall = AMDGPU::isC